How to deal with an input signal with unknown size in VHDL code

[MSAKARIM]

I'm working on (IPV4) the ipv4 packet as shown in Fig. the partition named " Data " has variable size according to the received payload
I want to write a VHDL code to receive the whole packet and then split it into two parts: header bits and data bits.
How can I deal with input signal with variable size?

 

[ads-ee]

Are you saying you are getting all 1500 or so potential bytes in single vector? Usually Ethernet IP cores will give you something 32-bit data on each clock cycle not the entire payload in one clock.

 

[TrickyDicky]

Read the Packet length part of the header, then you know how long the data is.
Just to make your life more interesting, the "length" field of the header also tells you how long the header is - the header can be between 20 and 64 bytes.
How are you getting the IPv4 packets in an FPGA? Usually, if you're using a MAC IP, you'll get the ethernet frame to deal with as well. That can be between 14 (no VLAN) or 18 (With Vlan) bytes before you get to the IPv4 bit (even more if you're able to receive double tags). Good luck....

 

[dpaul]

How can I deal with input signal with variable size?

It is of variable size but not of unknown size.

I take here the example of Xilinx TEMAC IP core. This IP has two signals rx_statistics_vector(27:0) and rx_statistics_vector_valid. When the _valid is high (after a frame has been successfully rx by the MAC), the bits rx_statistics_vector(18:5) gives you the frame length in bytes.
The Header size is already known to you. So with these info you can perform your background work with the frame.

If you are not dealing with Jumbo frames, then your rx frm can have of 1518 bytes, so you can buffer the rx frm in a rx_fifo of such size.

I do not know which Eth MAC core you are using, but such signals makes working a bit easy.

 

[MSAKARIM]

Are you saying you are getting all 1500 or so potential bytes in single vector? Usually Ethernet IP cores will give you something 32-bit data on each clock cycle not the entire payload in one clock.

Yes, but they aren't 1500bit, Data isn't determined

Are you saying you are getting all 1500 or so potential bytes in single vector? Usually Ethernet IP cores will give you something 32-bit data on each clock cycle not the entire payload in one clock.

Yes, but they aren't 1500bit, Data isn't determined

 

[TrickyDicky]

You dont say how the packets are arriving? are they over a specific interface? most will have some kind of streaming interface - is that how the packets arrive?

 

[ads-ee]

Yes, but they aren't 1500bit, Data isn't determined

Yes, but they aren't 1500bit, Data isn't determined

You're making this very unclear.

I was asking if you get the Ethernet packet as a broadside multi-byte vector of all the bytes in the entire packet.

I asked this question because of the first post where you asked about input signals with varying widths. That made me think you are getting the entire packet as a single input for each packet.

If you aren't getting the packet is such a strange way then the other replies tell you what you need to know.

 

[FvM]

Is it a VHDL language exercise or a real data processing problem?