How to create HSPICE netlist???

[etrobin]

starrc sp netlist format

Hello, all,

I would like to know how to create a HSPICE netlist(.sp) if I got library & model for it??? What I want to do is to run transient analysis of some circuit of verilog netlist which used for post-simulation!!! Moreover, if I run HSPICE by input schematic, can I got the same analysis as real chip???
Thank you for advise!!!

etrobin

 

[qslazio]

the syntax of verilog netlist is complete different from that of hspice

you should do STA and get sdf file and back annotate for your verilog netlist
BTW: The tool that do post simulation is still VCS or VerilogXL

 

[etrobin]

Thank you for reply!!!
I know how to do sta/post-simulation with verilog netlist & sdf!!!
I just want to run HSPICE, but have no idea about how to input a netlist (.sp)??
Any advise???

etrobin

 

[wein]

you can use synopsys nanosim simulatiom your design base on spice.

 

[rakko]

easiest way to create spice netlist from your design is to read it into cadence virtuoso and then tell cadence to write the spice netlist. If you have access to cadence tool (icfb tool) and want to do this let me know and i will send you the procedure for doing this.

 

[kelvin_sg]

When you do HSpice simulation, you shall ask your
Place & Route vendor for the CDL netlist. After they
do P&R, the layout tools can extract some transistor
models and wire resistance/capacitance values.
These values are used for transient simulation.

CDL netlist is different from Verilog.

 

[haosg]

you can run starRC to extract parasitics, it generally is spef file that are similar to spice.
you can run hsim or nanosim to do sub-spice -level simulaiton.
I think the hspice also can read the file,but the simulation would too long.
for digital design, the nanosim and hsim is sufficient.

 

[markty]

Since u want to do a post simulation, I think u can extract the netlist from the layout.

 

[tony_taoyh]

I advise two methods, hope helpful for you.
(1) If you need accurate result, then you need to use the GDS to do the RC extraction, then use the
generated RC Hspice netlist to do the transistor level simulation.

(2) If you just need run a Hspice simulation, without high requirement on the accuracy. Then you can use "nettran" (in Heculus) or "v2lvs" (in Calibre) to transform the verilog netlist into the Hspice netlist. To keep the accuracy, some CShunt may be added according to the technology library used.

Good luck...

 

[amedfaraz]

easiest way to create spice netlist from your design is to read it into cadence virtuoso and then tell cadence to write the spice netlist. If you have access to cadence tool (icfb tool) and want to do this let me know and i will send you the procedure for doing this.

Hey,
I badly need your help!
I have access to cadence tool, I will appreciate if you can send me the procedure to create spice netlist from the design from cadence virtuoso(I have the synthesized verilog netlist of my design)

 

[keith1200rs]

You should start a new thread rather than digging up a 7 year old one.

Keith.