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How to creat IP core in Quartus?

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vidivici.world

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Hi, all!
I want to package my own HDL code into IP core (just like NGC or edif files in Xilinx) in Quartus, but cannot find the proper tool. Can anybody help me? Thanks!
 

Brownout

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NGC and EDIF are just netlist files generated from synthisis tools. Altera generates netlist files (.vo and .vho ) useing Netlist Writer. What exactly are you wanting to do?
 

vidivici.world

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NGC and EDIF are just netlist files generated from synthisis tools. Altera generates netlist files (.vo and .vho ) useing Netlist Writer. What exactly are you wanting to do?
I mean that Packaging my HDL code into some kind of file format(IP) that can be recognized by FPGA tools, so that another person can reuse the IP I creat, but don't know the exact algorithm or implementation in it, like a blackbox, only function and ports can be seen from outside. Just like the way Quartus does to his Multiplier or DSP IP, so we can use it through MegaWizard Plug-in Manager.
 

Brownout

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In that case, you can just use the database files from synthesis. Neither EDF or NGC do what you're talking about. If you want to protect your IP, then just offer precompiled modules. You can document the interface for your customer.

At least that's the only way I know to do it.
 

vidivici.world

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In that case, you can just use the database files from synthesis. Neither EDF or NGC do what you're talking about. If you want to protect your IP, then just offer precompiled modules. You can document the interface for your customer.

At least that's the only way I know to do it.
Thanks a lot.
But would you please explain it in detail? I assumed that the precompiled modules you mean is the DB folder under project folder, containing .tdf files etc. Say another user has many modules, and your design is one of them, so how to make use of the precompiled modules and integrate them into his project, to successfully compile them?
Really don't know how to do that, thanks for your time and patience:)
 

seesea11

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processing-> start-> start VQM writer. but this item may be grayed out for some device families.
i use Synplify instead of quartus.
 

vidivici.world

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processing-> start-> start VQM writer. but this item may be grayed out for some device families.
i use Synplify instead of quartus.
Thanks, but I have discovered another way---just export the module into .qxp files, then the user will have no idea of your HDL code.
 

Brownout

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Glad to hear you have a solution. I noticed recently that my nios ii verilog file from Altera is incripted, and cannot be read in an editor. Somehow, the software can read it. I don't know if they offer the encription service to users though.
 

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Clearly encryption service is not supported by Quartus, it's just limited to its own IP cores.
 

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