how to couple with the ram/rom in primetime??

[ls000rhb]

q:how to couple with the ram/rom in primetime??

i write blank modules for ram/rom in RTL netlist.After synthesis and P&R,i generate a postlayout gate netlist from Apollo.Read the postlayout netlist into Primetime,i find the ram/rom is still black box.i think the timing infromation of the ports in ram/rom may be loss.

q:how to couple with the ram/rom in primetime??

 

[jjww110]

there are ram and rom tming model in the library,in pt, you should read those models , and pt will check timing about the interface with rom and ram.

 

[spauls]

put in link library (db)

 

[johnz]

memory compiler generate lib file in asic design, then use dc or pc to generate db file from lib.