How to correct the setup and hold time violations in Physical Design flow?

[smith_kang]

Hi all,
Can anybody tell me how to correct the setup and hold time violations in Physical Design flow.Which time should get more preference and why.Kindly explain how to correct these violation or suggest some good reference.

Thanks,

 

[Thomson]

Re: Setup Hold time

(1) please strictly adhere to the design flow of the tool
(2) if you do design according to the design flow, then check whether you set the write constraints and consider it whether it's too strict
(3)otherwise you shall modify your design to make it match your timing requirements and even alter all the design RTL implementation if the timing is still not okay
(4) for the hold time it's easy and you may still ignore the violation when it's not too large and let this completed during the post-layout phase



Good Luck!

 

[brianhe]

Re: Setup Hold time

Change rtl is the last way. You can imporve the timing through ECO, that is modifiy the netlist directly.
Setup time is more critical. One possible reason may be the load at that point is too heavy. So you can resove it in two way:
1. Replace the driving component with more powerful driver.
2. Seperate the load into different groups. each group is driven by the same logic but different driving cell/buffer.

Added after 5 minutes:

Hi all,
Can anybody tell me how to correct the setup and hold time violations in Physical Design flow.Which time should get more preference and why.Kindly explain how to correct these violation or suggest some good reference.

Thanks,

Hold time is easy to be fixed. You can just add buffer. But pay attention to not add too much so that impact timing of next stage

 

[Thomson]

Re: Setup Hold time

one more thing shall be paid attention to the setup/hold timing check of the SYNCHRONIZER