How to convert the final ncd file to verilog and simulate it

[fa1364]

ncd to verilog

hi.
please tell me how can I convert the final ncd file to verilog and simulate it in modelsim?

 

[echo47]

ncd to verilog

I run Xilinx ISE from the command line, not Project Manager. I use this command to read the routed netlist of my "top" project from my "build" folder, and write the post-route Verilog to a folder named "post":
netgen -sim -intstyle silent -ofmt verilog -ism build\top -ngm build\top_map -w -dir post