Thanks sarath
I have this documets...but what im looking for is something else...
I want a kind of example, with testbench covering different test cases(vhdl if possible) ...and final TCL script which controls this test bench...if u have any material, any link please upload.
Thanks..
Kind of example------------------from asicworld.com
module counter_tb; // say counter design we have n this is its testbench
reg clk, reset, enable;
wire [3:0] count;
counter U0 (
.clk (clk),
.reset (reset),
.enable (enable),
.count (count)
);
initial
begin
clk = 0;
reset = 0;
enable = 0;
end
always
#5 clk = !clk;
endmodule
///say i have reset n clock test case....
event reset_trigger; // now whts this "event"....in VHDL wht to use
event reset_done_trigger;
initial begin
forever begin
@ (reset_trigger);
@ (negedge clk);
reset = 1;
@ (negedge clk);
reset = 0;
-> reset_done_trigger;
end
end
initial
begin: TEST_CASE
#10 -> reset_trigger;
end
initial
begin: TEST_CASE
#10 -> reset_trigger;
@ (reset_done_trigger);
@ (negedge clk);
enable = 1;
repeat (10) begin
@ (negedge clk);
end
enable = 0;
end