How to control clocks gererated by on-chip PLL

[sycolegend]

Hi,
In our SOC, there're two clocks generated by an on-chip PLL. For the DFT design, we want scan in initial datas into all the DFFs via jtag IEEE1149, then capture and scan out the datas after the system clocks run one cycle. But how we can control the clocks just run one cycle and hold until we scan out all the datas through a Jtag interface.

 

[linuxluo]

hi,
I think what you want is the job of atpg tools should becoz what you want is at-speed test. I think ET,tmax can handle this situation.

 

[libing]

hi
generally,you can use dft compile to generate DFT chain , there are dft mode pin, what you should do is to control the dft mode pin , maybe you use jtag to control dft scan . you can use dc compiler command to insert jtag .

 

[ls000rhb]

insert_scan maybe help!! good luck!!