How to constraint the PLL when we do STA?

[straw]

How do we constraint the PLLwhen we do STA?
Who have the book about this?
Thanks a lot

Added after 5 hours 1 minutes:

the timing verification book has the content about PLL.who have this book?
thanks

 

[gavinsun]

You mean create clock on pll, set clock source latency for pll output clk or other item???

 

[ivlsi]

So, how should be checked a design, which is driven by PLL, during?

How should PLL block be constrained if it's a part of the design?

Thank you!

 

[dick_freebird]

Every PLL will have a range of static timing error (offset
variation, loop amp gain, kV) and I would think it useful to
create corner timing cases expressing that range (plus a
bit of design margin, perhaps to cover the excursions of
phase / freq during any phase slewing). Any relation to
other signals (such as the source data in a CDR app) will
want to be expressed or embedded.

 

[ivlsi]

Thank you dick!
How should all the PLL staff be translated to the timing constrains?
Thank you!