Which are the 2 clocks you are talking about.(de & dclk). I see a total of 4 clocks in the design which have to be provided constraints...2 primary and 2 generated
I don't think this is good practice. If de violates the setup time of the first FF, its output could go metastable. Maybe the second FF sees that metastable state as a zero (fine), but maybe it sees it as a one. That's going to mess things up.
I don't think this is good practice. If de violates the setup time of the first FF, its output could go metastable. Maybe the second FF sees that metastable state as a zero (fine), but maybe it sees it as a one. That's going to mess things up.
The first thing I thought when I saw the OP's schematic and waveform was this is going to result in a RE-SPIN.
If this circuit is supposed to detect the rising edges (hclk) of de using a dclk that turns on and off then based on the implementation that dclk better be synchronous with de. Based on that timing diagram it seems that dclk is generated from some logic or gated clock, so it's going to have skew from de even if both dclk and de are generated from the same base clock. My advice rethink what you are doing and look for a better solution.