Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to constrain design with generated clock. (DC)

Status
Not open for further replies.

taisun9

Newbie level 3
Joined
Jun 9, 2006
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,325
I have implemented a clock divider and a controller as the figure shows.
The datapath of the controller block is shown in the right part.
The divider can produce slow clock with preiod of 1,2,4,8... times of the fast clock.
The problem is I don't know how to constrain the clocks in my design with Design Compiler.
I have tried:
(1) create clock at only fast clock, the synthesis speed is quite slow.
(2) create clock at fast clock and a generated clock at slow clock.
(3) create clock at the two I/O ports of the controller.
Most methos I used result in very slow speed during synthesis except the (3) one.
Does that come from the "Multiple Clock Domains" (slow and fast clock)?
(I think that DC tries to check and solve timing between those DFFs clocked by the two different clocks)
I don't know which one can correctly constrain the design during synthesis.
I have also tried to use create_generated_clock but I can't correctly indentify clock latency from the source "fast clock" since the single "fast_clk" passes different paths when divider produces different clocks.
I have also searched many documents about generated clocks but most of them are about simple generated clock, i.e., divided by a constant.
Please kindly help! Thank you very much! :cry:
 

wkong_zhu

Full Member level 3
Joined
Nov 13, 2004
Messages
174
Helped
4
Reputation
8
Reaction score
0
Trophy points
1,296
Activity points
1,293
In my case, if you don't care the paths between the 2 different clocks, you can define them as 2 independent clocks and set_flase path between them. I have done a job like this.
But if timing requirements is needed between the 2 clock domains, You may use generated clock. select one divisor number that can meet all the timing requirements, It must be done case by case.
 

taisun9

Newbie level 3
Joined
Jun 9, 2006
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,325
wkong_zhu said:
In my case, if you don't care the paths between the 2 different clocks, you can define them as 2 independent clocks and set_flase path between them. I have done a job like this.
But if timing requirements is needed between the 2 clock domains, You may use generated clock. select one divisor number that can meet all the timing requirements, It must be done case by case.

Thanks for replying. This is the first time I encounter this multiple clock domain case. Since I am afraid that the chip fails after tapping out, I need to do very careful analysis for its timing. I am not sure if the design is safe if I define them as 2 independent clocks. The way I do now is:

(1) define fast_clk as a clock
(2) define slow_clk as a generated clock with source coming from fast_clk
I use multiply_by 2, which is its fast speed.

To use a generated clock, the problem is that I also don't know if I need to define more precise relations between them (eg, clock_latency). It's also hard to find those relations as I said that the paths through Divider are many.
Any hint is welcome!
 

yaseen1

Member level 1
Joined
May 20, 2006
Messages
41
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,582
As per knowledge we never Constraint any design with Generated clock
 

taisun9

Newbie level 3
Joined
Jun 9, 2006
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,325
yaseen1 said:
As per knowledge we never Constraint any design with Generated clock
Really? If I don't constraint them, how do I tell the synthesizer to check the timing (setup/hold time) of my controller?
 

spauls

Advanced Member level 2
Joined
Dec 17, 2002
Messages
524
Helped
26
Reputation
52
Reaction score
9
Trophy points
1,298
Activity points
3,354
Hello Taisun,

You can constrain with Generated clocks it is completely safe.
You need to get the latency of the master clock, it will automatically perculate to lower level,
Else you can constrain with set_max_delay option.
You have to set a multi cycle path between fast and slow clock.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top