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How to connect transistor bulk to its source in CMOS layout?

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m_mosazadeh

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CMOS layout problem

hi
I want to connect a transistor bulk to its source.How can I do this in layout of nmos transistor?
 

CMOS layout problem

I nwell cmos technology, the bulk of nmos should be connected to the lowest voltage level ( typically gnd).
 

Re: CMOS layout problem

it depond you processs

if it is twin well process, you can connect the bulk and source together.

True cmos process, if psub, the bult only be connect to the lowest voltage level
 
CMOS layout problem

otherwise, you have pwell process, at that time, you can connect your bulk to the its source.

otherwise, as sunking said, the bulk only be connect the lowest voltage level, it means, when a NMOS transistor is connected to GND, its bulk can connect to the source.
 

CMOS layout problem

the bulk often connect to source.it's layout is use a cont connect nsd with pring
 

CMOS layout problem

make another p+ diffusion and add a contact
then connect them with mental 1
 

CMOS layout problem

if you can using the other layer DNTUB it's very easy
or you have the pwell
 

Re: CMOS layout problem

Draw P+ contact array as close to the nmos transistor as the design rules allow and connect this to the source.
 

Re: CMOS layout problem

in a pwell it is easy
or you can only tie them to ground
 

CMOS layout problem

That depends on your process.

As far as i know, u can not connect the bulk of nmos to the source(not ground) even in the twin well process. Because the sub is always p type.
 

Re: CMOS layout problem

in twin well process it is possible to connect source to bulk.
 

Re: CMOS layout problem

You can use Deep NWell. It seems can do this job.
 

Re: CMOS layout problem

Analog_starter said:
You can use Deep NWell. It seems can do this job.


It depends on the process. Not all processes support Deep NWell.
 

Re: CMOS layout problem

Colbhaidh said:
Draw P+ contact array as close to the nmos transistor as the design rules allow and connect this to the source.


right ,I agree
 

CMOS layout problem

normally ,connecting bulk and source is not good in analog layout.they are seperatly connected to respective power rails .
 

Re: CMOS layout problem

if the nmos on p-sub, they will be connected automatic
 

CMOS layout problem

In p-sub n-well processes,the bulk is always connected to gnd.
 

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