Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to connect transistor bulk to its source in CMOS layout?

Status
Not open for further replies.

m_mosazadeh

Member level 4
Member level 4
Joined
Apr 25, 2004
Messages
69
Helped
0
Reputation
0
Reaction score
1
Trophy points
1,286
Location
iran
Activity points
350
CMOS layout problem

hi
I want to connect a transistor bulk to its source.How can I do this in layout of nmos transistor?
 

Hughes

Advanced Member level 3
Advanced Member level 3
Joined
Jun 10, 2003
Messages
715
Helped
113
Reputation
226
Reaction score
26
Trophy points
1,298
Activity points
5,984
CMOS layout problem

I nwell cmos technology, the bulk of nmos should be connected to the lowest voltage level ( typically gnd).
 

sunking

Advanced Member level 3
Advanced Member level 3
Joined
May 25, 2004
Messages
873
Helped
70
Reputation
140
Reaction score
23
Trophy points
1,298
Activity points
6,283
Re: CMOS layout problem

it depond you processs

if it is twin well process, you can connect the bulk and source together.

True cmos process, if psub, the bult only be connect to the lowest voltage level
 

piao

Full Member level 4
Full Member level 4
Joined
Feb 12, 2003
Messages
221
Helped
12
Reputation
24
Reaction score
8
Trophy points
1,298
Activity points
1,517
CMOS layout problem

otherwise, you have pwell process, at that time, you can connect your bulk to the its source.

otherwise, as sunking said, the bulk only be connect the lowest voltage level, it means, when a NMOS transistor is connected to GND, its bulk can connect to the source.
 

qutang

Full Member level 5
Full Member level 5
Joined
Oct 25, 2004
Messages
305
Helped
9
Reputation
18
Reaction score
3
Trophy points
1,298
Activity points
1,581
CMOS layout problem

the bulk often connect to source.it's layout is use a cont connect nsd with pring
 

qslazio

Full Member level 3
Full Member level 3
Joined
May 23, 2004
Messages
175
Helped
18
Reputation
36
Reaction score
7
Trophy points
1,298
Activity points
1,420
CMOS layout problem

make another p+ diffusion and add a contact
then connect them with mental 1
 

yeewong_su

Advanced Member level 4
Full Member level 1
Joined
Oct 12, 2004
Messages
119
Helped
5
Reputation
10
Reaction score
3
Trophy points
1,298
Activity points
803
CMOS layout problem

if you can using the other layer DNTUB it's very easy
or you have the pwell
 

Colbhaidh

Full Member level 6
Full Member level 6
Joined
Aug 10, 2004
Messages
393
Helped
141
Reputation
280
Reaction score
98
Trophy points
1,308
Location
Scotland
Activity points
3,756
Re: CMOS layout problem

Draw P+ contact array as close to the nmos transistor as the design rules allow and connect this to the source.
 

layes2

Full Member level 4
Full Member level 4
Joined
Dec 3, 2004
Messages
230
Helped
10
Reputation
20
Reaction score
6
Trophy points
1,298
Activity points
1,410
Re: CMOS layout problem

in a pwell it is easy
or you can only tie them to ground
 

markty

Member level 3
Member level 3
Joined
Dec 15, 2004
Messages
59
Helped
2
Reputation
4
Reaction score
0
Trophy points
1,286
Activity points
493
CMOS layout problem

That depends on your process.

As far as i know, u can not connect the bulk of nmos to the source(not ground) even in the twin well process. Because the sub is always p type.
 

m_mosazadeh

Member level 4
Member level 4
Joined
Apr 25, 2004
Messages
69
Helped
0
Reputation
0
Reaction score
1
Trophy points
1,286
Location
iran
Activity points
350
Re: CMOS layout problem

in twin well process it is possible to connect source to bulk.
 

Analog_starter

Advanced Member level 4
Full Member level 1
Joined
Nov 15, 2004
Messages
113
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,296
Activity points
1,111
Re: CMOS layout problem

You can use Deep NWell. It seems can do this job.
 

lakeoffire

Member level 2
Member level 2
Joined
Dec 10, 2002
Messages
53
Helped
3
Reputation
6
Reaction score
1
Trophy points
1,288
Activity points
426
Re: CMOS layout problem

Analog_starter said:
You can use Deep NWell. It seems can do this job.


It depends on the process. Not all processes support Deep NWell.
 

jianbinma

Newbie level 4
Newbie level 4
Joined
Jan 22, 2005
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
58
Re: CMOS layout problem

Colbhaidh said:
Draw P+ contact array as close to the nmos transistor as the design rules allow and connect this to the source.


right ,I agree
 

omsi

Member level 5
Member level 5
Joined
Jan 24, 2006
Messages
93
Helped
7
Reputation
14
Reaction score
6
Trophy points
1,288
Location
London
Activity points
2,105
CMOS layout problem

normally ,connecting bulk and source is not good in analog layout.they are seperatly connected to respective power rails .
 

yaxazaa

Advanced Member level 4
Full Member level 1
Joined
Nov 13, 2004
Messages
117
Helped
5
Reputation
10
Reaction score
2
Trophy points
1,298
Activity points
902
Re: CMOS layout problem

if the nmos on p-sub, they will be connected automatic
 

jinxingsun

Member level 5
Member level 5
Joined
Aug 28, 2005
Messages
82
Helped
5
Reputation
10
Reaction score
1
Trophy points
1,288
Activity points
1,876
CMOS layout problem

In p-sub n-well processes,the bulk is always connected to gnd.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top