How to connect a control signal to DFFs clock enable port?

[nwu]

gate clock problem!

hi all:
there has a signal to control a clock that will be used in a DFF.
so i want to make this control signal connected to DFF's clock enable port,
how do you deal with this problem?.

 

[jelydonut]

Re: gate clock problem!

If your using the clock enable your not really gating the clock.. as long as you can garrentee that the enable is clean before the clock edge then you should be ok..

always @(posedge clk)
if(rst)
x <= 1'b0;
else
if(enable)
x <= y;

jelydonut

 

[papyaki]

Re: gate clock problem!

Hi

If your D flip flop use the rising edge of the clock signal, then sample the enable on the falling edge of the clock signal (through a DFF) before driving the enable input of your first DFF.

 

[skynet]

Re: gate clock problem!

I don't think there is any clocking enable at any dff.. that is data enable pin available at dff.. anyway depend i believe that depend on what kind of technology is avaialable for your synthesis. to perform gate u can do like this

wire gated_clock;

assign gated_clock = clk & en;

always @(posedge gated_clock or negedge rst)
begin
if (!rst)
q <= 0;
else
q <= d;
end

hope this help