To understand the circuit you posted, best is to understand the basic principles of analog design mentioned by others posted earlier here or by me posted below.
What is the critical issue in CMOS analog design? Flicker noise and mismatches.
Someone mentioned Flicker or 1/f noise that predominates any other noises at low frequencies. That's very good!
Mean Vn² = (1/f).K/Cox.W.L, thus larger L and/or W to decrease 1/f noise. This is one of the many reasons why some low-speed or low-frequency designs still prefer to use 0.25 or 0.35 or even 0.5 since there is no need to invest so much money for 0.13 if only low-noise performance is needed, and not high-speed.
However 1/f noise is not a serious issue at high-frequency analog circuits. It is critical for Low IF receiver and low-frequency/low-speed designs, however.
Despite this 1/f noise, it is peak at DC, thus high-frequency circuits aren't not spared. Therefore in high-frequency circuits, DC/static/quiescent power dissipation must be reduced to the minimum, especially in the biasing.
Gm is directly proportional to W/L. Larger L decreases Gm, thus reduces CMRR, PSRR. This is not very wise. The choice is either to decrease L or increase W.
Smaller L also primarily aims to push maximum bandwidth, increases output impedance, density and compatibility with digital. Relatively, decreasing L allows W to be decreased too, by same proportion or ratio, thus increases maximum bandwidth. Decreasing L is also used when W becomes so large as in a wide transistor that the use of a interdigitated transistor is unavoidable.
Analog designers have to compromise W/L either increasing W or decreasing L.
There is however one drawback of increasing W - increased parasitics Cgd and Cgs that increase Miller Effect, thus limiting maximum bandwidth.
Theoretically smaller L looks good but in practice, it is not easier to achieve due to matching problems.
You normally see performance analog circuits still done at higher L at 0.25 or even 0.5. The reason being that it is harder to match, due to process variation, in smaller L. Matching is better at higher L.
With the above reasons mentioned, analog is usually not done below 0.18-µm, despite attempts in 0.13-µm and even 90nm however with very bad matching.
Another reason is the model used. Analog designs these days are done with short-channel devices, despite the scaled-reduction in Vdd to reduce short-channel effects. If you still think that you are using long-channel devices, your design will never work. Models offered to you by foundry is a very deterministic factor. It affects your HSPICE simulation and confidence to succeed.
Right now, TSMC and UMC offers the best models for analog because of very low process variations. If you use IBM, STMicro, Chartered, NEC, or even AMI, your designs are likely to fail.
In digital where a minimum-sized transistor can achieve ratioless CMOS logic without using larger transistors unless for driving or large fan-out purpose. This favours reduction in area, parasitics, delay and loading, for high density, speed and lower power dissipation.
In analog, the art is different. We play with W/L for Gm, CMRR, PSRR, SNR, Ft, ro, noise reduction, slew rate, biasing and power consumption, feedback & stability, and many more tradeoffs.
Unlike digital, there is no noise margin to tolerate noises and offsets in analog. Every little variation causes error that must be compensated or tuned for, else it gets amplified or accumulated to the output.