Something that I have done untill now, is shown in the attached snapshot. I have generated the IP core AXI UART16550 as an Out-of-context module along with mu top file (top file includes my counter). But after synthesis and implementation, I do not see the UART module and I do not know how should I define the outputs of counter to be sent to the UART and what constraints are required to make the UART run and send the counted values to the PC to be seen in terminal???
From the screenshot it is apparent that you have just generated the IP core AXI UART16550 and have added it to the project. Where have you done the actual connection of the IP with the module that would generate the data to be transmitted?
Keep aside the counter idea for now.
There are many tutorials as how "Hello World" can be printed at Putty/HyperTerminal using an AXI UART running on the FPGA. Implement that and study it. One you fully understand how the AXI UART exchanges data via the AXI i/f, then go for your counter implementation.
If you are scared about the complexities of AXI and C code running on a processor, you should follow what FvM says in #2.
Here is a helpful step by step:
https://reference.digilentinc.com/l...basys-3-getting-started-with-microblaze/start
Good, now that you know how to use make use of the UART and controlling it via s/w, this is what you can try.
1. Store the counter values in a register.
2. Make this reg readable by the zynq processing system (connect the reg to the bus).
3. Write C code to read this reg (at regular intervals) and send the read-out value/values to the UART.
4. So just as "Hello Word" is seen in the terminal, so should be the reg value/values (if everything is done properly).
Done!
make the GPIO an input only then. you can double click on the axi_gpio_0 block and change direction of the GPIO ports.
[DRC MDRV-1] Multiple Driver Nets: Net zynq_processor/gpio_rtl_tri_iobuf_0/IO has multiple drivers: zynq_processor/gpio_rtl_tri_iobuf_0/OBUFT/O, and prd_contr/p_reg_reg[0]/Q.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 //Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. //-------------------------------------------------------------------------------- //Tool Version: Vivado v.2016.2 (win64) Build 1577090 Thu Jun 2 16:32:40 MDT 2016 //Date : Thu Aug 17 13:09:32 2017 //Command : generate_target design_1.bd //Design : design_1 //Purpose : IP block netlist //-------------------------------------------------------------------------------- `timescale 1 ps / 1 ps (* CORE_GENERATION_INFO = "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=6,numReposBlks=4,numNonXlnxBlks=0,numHierBlks=2,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=1,da_board_cnt=2,synth_mode=Global}" *) (* HW_HANDOFF = "design_1.hwdef" *) module design_1 (DDR_addr, DDR_ba, DDR_cas_n, DDR_ck_n, DDR_ck_p, DDR_cke, DDR_cs_n, DDR_dm, DDR_dq, DDR_dqs_n, DDR_dqs_p, DDR_odt, DDR_ras_n, DDR_reset_n, DDR_we_n, gpio_rtl_0_tri_i, gpio_rtl_tri_i, gpio_rtl_tri_o, gpio_rtl_tri_t); inout [14:0]DDR_addr; inout [2:0]DDR_ba; inout DDR_cas_n; inout DDR_ck_n; inout DDR_ck_p; inout DDR_cke; inout DDR_cs_n; inout [1:0]DDR_dm; inout [15:0]DDR_dq; inout [1:0]DDR_dqs_n; inout [1:0]DDR_dqs_p; inout DDR_odt; inout DDR_ras_n; inout DDR_reset_n; inout DDR_we_n; input [31:0]gpio_rtl_0_tri_i; // NOTE this is an input only! input [31:0]gpio_rtl_tri_i; // Bi-directional on LED (should have been output only, oh well) output [31:0]gpio_rtl_tri_o; // bi-directional output output [31:0]gpio_rtl_tri_t; // bi-directional output tri-state // rest of file deleted as unimportant to the answer
Good, now that you know how to use make use of the UART and controlling it via s/w, this is what you can try.
1. Store the counter values in a register.
2. Make this reg readable by the zynq processing system (connect the reg to the bus).
3. Write C code to read this reg (at regular intervals) and send the read-out value/values to the UART.
4. So just as "Hello Word" is seen in the terminal, so should be the reg value/values (if everything is done properly).
Done!
Why do you have a tristate iobuffer on the net? I think you've specified the GPIO incorrectly and designated it as an output pin when it should only be an external port. I'm assuming that the prd_contr is instantiated outside this block design in a top/wrapper file as there is not a prtd_contr in the bd.
You probably specified the wrong dual channel GPIO interface as the input and output (the other one looks like it connects to some LEDs).
Here is an example done under 2016.2 with just a Zynq and a dual channel GPIO.
View attachment 140620
This produces the following top level .v file:
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 //Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. //-------------------------------------------------------------------------------- //Tool Version: Vivado v.2016.2 (win64) Build 1577090 Thu Jun 2 16:32:40 MDT 2016 //Date : Thu Aug 17 13:09:32 2017 //Command : generate_target design_1.bd //Design : design_1 //Purpose : IP block netlist //-------------------------------------------------------------------------------- `timescale 1 ps / 1 ps (* CORE_GENERATION_INFO = "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=6,numReposBlks=4,numNonXlnxBlks=0,numHierBlks=2,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=1,da_board_cnt=2,synth_mode=Global}" *) (* HW_HANDOFF = "design_1.hwdef" *) module design_1 (DDR_addr, DDR_ba, DDR_cas_n, DDR_ck_n, DDR_ck_p, DDR_cke, DDR_cs_n, DDR_dm, DDR_dq, DDR_dqs_n, DDR_dqs_p, DDR_odt, DDR_ras_n, DDR_reset_n, DDR_we_n, gpio_rtl_0_tri_i, gpio_rtl_tri_i, gpio_rtl_tri_o, gpio_rtl_tri_t); inout [14:0]DDR_addr; inout [2:0]DDR_ba; inout DDR_cas_n; inout DDR_ck_n; inout DDR_ck_p; inout DDR_cke; inout DDR_cs_n; inout [1:0]DDR_dm; inout [15:0]DDR_dq; inout [1:0]DDR_dqs_n; inout [1:0]DDR_dqs_p; inout DDR_odt; inout DDR_ras_n; inout DDR_reset_n; inout DDR_we_n; input [31:0]gpio_rtl_0_tri_i; // NOTE this is an input only! input [31:0]gpio_rtl_tri_i; // Bi-directional on LED (should have been output only, oh well) output [31:0]gpio_rtl_tri_o; // bi-directional output output [31:0]gpio_rtl_tri_t; // bi-directional output tri-state // rest of file deleted as unimportant to the answer
View attachment 140621
As you can see the gpio_rtl_0 port is an input only.
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