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How to configure the PCI interface core from opencores?

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buenos

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opencores pci

has anyone use PCI interface core from opencores?

what do i have to configure, and in which files?

when i try to sintesize with ise 8.2 it founds errors. i always developed my own vhdl code, but now i have to reuse a code written by another person.

does anyone have that core modified to target only? i hope it needs less logic resources.

can i get a working ise project of that, or edif files? i think i would use it in the Altium Designer Nexar to connect it to the whisbone bus and to the peripheraals what i want to use (CAN, GPIO). 32bit, 33 and 66MHz, on Spartan 2 and 3 too. (4 edif files?)
 

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