How to compile encrypted verilog file in Modelsim?

[rezwanh]

I am using a 3rd party DDR3 SDRAM IP and all I got is a verilog protected .vp file and verilog header file .vh. I found following command in modelsim manual to protect a verilog file(you need to use `protected and `endprotected pragma in your verilog code) but I don't know how to compile a protected file.

vlog +protect xxxx.vp

I am wondering if anyone knows how to compile this .vp file.

 

[yura717]

vlog +protect xxxx.vp

This command Will create protected file .... its not used to compile your design.

 

[aruipksni]

This command Will create protected file .... its not used to compile your design.

vlog *.vp

???

 

[yura717]

You can compile encrypt.vp just like any other verilog file