Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to compensate my LDO ?

Not open for further replies.


Junior Member level 1
Feb 4, 2009
Reaction score
Trophy points
Activity points

After reading about this a bit I understand one way to compensate an LDO is to ensure the internal pole (error amp output pole) is the dominant pole, such that the LDO output pole which varies with the output current load doesn't have a strong effect on the stability (phase margin).
Now in my case (see attached schematic) the output pole is at a very low frequency (70mHz) with no load because I have a 2uF output cap and I'm trying to keep the quiescent current low so I have a 1.7Mohm resistor divider (hence output impedance). If I want to place the error amp pole at an even lower frequency, that will require a very large internal cap (even with Miller effect) and I don't have the room for that (too costly).
What would be an alternative way to compensate this LDO?

Re: LDO compensation

PSG said:
What would be an alternative way to compensate this LDO?
An LDO normally always has the dominant pole at the output - because of the relatively large filter capacitor. This low frequency pole generates a phase shift of -90°, which doesn't hurt as long as all other non-dominant poles are (far) out of the (compensated) amplifier's vu=0dB bandwidth.

Hence the worst case stability problem arises at max. current load and min. output capacitance, because this load configuration shifts the dominant pole furthest out to high frequency - and possibly too close to the next non-dominant pole.

The counter-measure is either to shift the next non-dominant pole(s) further out, or to decrease the closed-loop gain in order to bring the vu=1 bandwidth closer to the dominant (output) pole, by this alleviating additional phase shift caused by the next non-dominant pole. This last measure of course decreases the regulation accuracy and bandwidth.


    Points: 2
    Helpful Answer Positive Rating
Re: LDO compensation

If the LDO output comes to a pin , then large external capacitor use is possible and hence the output is made as a dominant pole.Such architecture has PMOS output transistor (high output impedance , Rds) and worst case for stability at high load currents ( low output impedance , 1/lambda*Id).

This architecture will have a good loop gain and hence good PSRR and regulation.

If the LDO output does not come out as a pin , then the output is made as the non dominant pole and some internal node is made as dominant with few pF of onchip cap.It is beneficial to have NMOS mother transistor as output device (low ohmic , 1/gm output impedance).This architecture will have less loop gain and hence less PSRR and regulation , generally low bandwidth.

LDO compensation


Acturally, I cannot fully understand the circuit. especially about the second differential pair. Could you tell me the function of that? Looks like you have a lot of amplifier stages, which can easily cause stability problems.

What I noticed is the way you did AC simulation. An AC source is directly insert into the loop. But the both terminal of the AC source is high impedance node. You may not get accuracy AC simulation results.

Re: LDO compensation

totally agree with jwfan, I'm clearly seeing 3 amplifying stages, which are completely unnecessary (and prohibitive for stability issues) on LDOs. Also, power pmos gives around 20dB of extra gain (which is bad because it multiplies the parasitic capacitance due to miller effect as well). Aditionally, you're test circuit for open loop AC response is wrong. And you're using a current source and a a resistor to simulate the load. You only need a current load for that purpose, since it will simulate the impedance variation since output voltage should be fixed.

To simulate you open loop AC response you should break the loop using a large inductor (@ Lmax) to mantain the proper DC op point and feedback the signal through a large capacitance (@ Cmax) to create a virtual wire in AC response.

Other thing, the fist single amplifying stage is not necessary, I mean, how much gain do you wanna obtain ? 80 dB is easily achievable with a two stage, cascode or folded-cascode topology, and that's enough gain to guarantee proper line and load regulation for most LDO apps.

What is your max output current ? It seems like your pmos aspect ratio is 200 in a 0.5 tech. I can assure you that aspect ratio wont give you any currents above 1mA, so if you're pushing more than that, the ouput impedance of the pmos on AC will be significant. And also you should take into account the Rds_on.

Finally, contrary of what dhasmana says, worst case stability is on low load currents, not high, where output impedance is greater and the output pole Ccomp*Rout goes to lower frequencies, causing stability problems

Not open for further replies.

Part and Inventory Search

Welcome to