how to comment out any blocks in cadence?

[shanmei]

Hi,

Is there any way to comment out the blocks in cadence as in matlab simulink environment?

Some blocks or wire we need to leave for the next step simulation, so I can temporarily leave it on the schematic window, but the netlist will not include those blocks.

any idea?　Thanks.

 

[dick_freebird]

I can suggest making an alternate view (such as, if you
use "schematic" for designs, cmos.sch or cmos_sch are
often unused but recognized as valid switch-views).
In these views, put nothing but pins matching the
symbol and "real" schematic. Now for your simulation
testbench create a config view (hierarchy editor) if
you have not already. Then open simulation session
from the config view and use the hierarchy editor to
assert that the cells you want to "dummy" should use
the alternate view with no content. This should give
nothing in the netlist if you are flat-netlisting, it may
give empty subcircuits if you use hierarchical I guess.
What the upshot of that might be, I couldn't say -
when I used Cadence our default setup was all flat.