Xilinx advertizement or datasheet says about the size of FPGA as System Gate.
Does anyone know how to come up with the calculation of the system gate?
The largest Virtex-II XC2V8000 is about 8 M sytem gates.
Does this mean I can implement 8M logic gates? I guess this is definitely not possible.
I too want to find out how to give an exact account for the system gates for a long time.
I know that System gates = Logic Gates + Block Ram bits "+ Routing resources?".
For reference, check Virtex-E datasheet. It describes both System gates and Logic gates saperately.
For XC2V8000, 8M logic gates certainly is not possible. Around 1.2-1.5M Logic gates is my estimate, but it mainly depends on your design.