how to close timing only with typical timing library under cmos 0.8um process

[macaren]

now, the foundry only provide the typical timing library because the 0.8um is an old process. and my layout design tool is "encounter". and no rc model. any suggestion?

 

[phoenixpavan]

Hi macaren,

In Synopsys tools we can specify derating factors..Maybe a similar provision is available in SOC..check it

cheers,

 

[yadavvlsi]

Yes, You can set derating factor in Cadence SOC Encounter.!

 

[macaren]

yes, I can set timing derate to contain all the cases. althou they are not accurate, but can be a subsititute. if set a larger range, maybe introduce more cells and power. and how to calculate the wire delay? for dsm process, there are QRC techfile or itf files to extract them accuratly. how about the wire delay for the .8um process? thanks

 

[lostinxlation]

wire delay is less significant with 0.8um. back in a day that 1um process or so was state of the art, not many people cared about wire delay.
With TT lib only, your option is pretty much derating only.

 

[macaren]

yes, the wire delay can be ignored. can anyone give a comparision with the cell delay, and the wire lenght impact etc. what is the margin should be set?
for set timing derate. max corner is not importan when I can down my clock. buf for the min corer, maybe introduce much more delay cells.