:?:How to clock such high performance ADCs?

[DZC]

I found ADI have release the AD9461(16-bit,130Msps),also TI ADS5474(14-bit,400Msps).
In sampling theory the clock rms jitter should be less than 50fs?
Is there any equipment that can offer such low jitter clock?
How do we generally clocking such high performance ADCs?

 

[n1cm0c]

They generate the sampling clock internally using a PLL, I suppose. It's likely that you should supply a low-phase noise differential clock signal of say 20 to 80 MHz and they have an internal clock multiplier that generates the sampling clock...

The ADI part is described in a JSSC publication, I think. They don't have a S/H before the first stage of the pipelined ADC.

 

[DZC]

But is it noise to embeded the PLL in to a ADC?