Ok, this is my most origin code to declare BRAM and it is really synthesized into RAM block!
Code:
process (CLK)
begin
if (CLK'event and CLK = '1') then
if (ENABLE = '1') then
if (WRENABLE = '1') then
BRAM(conv_integer(ADDRESS(13 downto 0))) <= DATA_IN;
end if;
DATA_OUT <= BRAM(conv_integer(ADDRESS(13 downto 0))); --if correct, cache out
end if;
end if;
end process;
The problem is now i want to reset~!! means when reset is '0', set all RAM to '0'
so i add a reset code
Code:
process (CLK)
begin
if (CLK'event and CLK = '1') then
if (RESET = '0') then
BRAM <= (others => (others => '0'));
elsif (ENABLE = '1') then
if (WRENABLE = '1') then
BRAM(conv_integer(ADDRESS(13 downto 0))) <= DATA_IN;
end if;
DATA_OUT <= BRAM(conv_integer(ADDRESS(13 downto 0))); --if correct, cache out
end if;
end if;
end process;
or
Code:
process (CLK)
begin
if (RESET = '0') then
BRAM <= (others => (others => '0'));
elsif (CLK'event and CLK = '1') then
if (ENABLE = '1') then
if (WRENABLE = '1') then
BRAM(conv_integer(ADDRESS(13 downto 0))) <= DATA_IN;
end if;
DATA_OUT <= BRAM(conv_integer(ADDRESS(13 downto 0))); --if correct, cache out
end if;
end if;
end process;
BOTH also become unsynthesizable! The ISE is hanging and showing the process is running and i already wait for an hour.. still running.. seems like hanged. Then I just need to stop the synthesizer..
I suggest to consult the respective FPGA datasheets. Block RAM can be written one memory location per clock cycle. This also applies for intended reset operation. There's no way to reset the memory array in a single clock cycle. The memory content will be asynchronously reset (or set to a specifies pattern) at power on. Runtime reset would need a state machine, addressing the memory sequentially.
check the XST user guide. This manual is helpful for BRAM/SRL/DSP48 coding styles. It is not exaustive though -- there are other ways to write code that will also work.