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How to clear PRE DRC(D1,D2,D3,D10,D11,D12,D15,D20) violations

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RAKESH E.R

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Dear sir,
i have only 2 clocks in my project those are System_Clock and SCK_s, those two can i control by using this declarations written below? what are the other things that i have to add before creating the protocol? i am not getting any error instead its accepting all the signals which i have given but none of the violations are solving..

set_dft_signal -view exist -type ScanClock -timing {45 55} -port System_Clock
set_dft_signal -view exist -type ScanClock -timing {45 55} -port SCK_s

Even after defining these 2clocks i get violatons below:
-----------------------------------------------------------------
Begin Pre-DFT violations...
-----------------------------------------------------------------
Warning: Clock input CK of DFF u97_interface_mux_cntrl/u7_interface_top/u0_ahb_apb_bridge1_top/u1_DW_apb_timers_top/U_tim1_timer_reg_8_ was not controlled. (D1-1)
Information: There are 503 other cells with the same violation. (TEST-171)
Warning: Set input SN of DFF u97_interface_mux_cntrl/u7_interface_top/u0_ahb_apb_bridge1_top/u0_DW_apb_top/U_DW_apb_ahbsif_hready_resp_reg was not controlled. (D2-1)
Information: There are 1309 other cells with the same violation. (TEST-171)
Warning: Reset input RN of DFF u97_interface_mux_cntrl/u7_interface_top/u0_ahb_apb_bridge1_top/u0_DW_apb_top/U_DW_apb_ahbsif_pwdata_int_reg_29_ was not controlled. (D3-1)
Information: There are 19405 other cells with the same violation. (TEST-171)
Warning: Clock System_Reset connects to data input (D) of DFF u97_interface_mux_cntrl/u7_interface_top/u2_i2c_spi_ahb_master/u2_ss_spi_top/inst_src_sync_spi_rx/data_reg_reg_60_. (D10-1)
Information: There are 63 other cells with the same violation. (TEST-171)
Warning: Clock System_Clock connects to clock and data inputs (CK/D) of DFF u97_interface_mux_cntrl/u7_interface_top/u0_ahb_apb_bridge1_top/u4_DW_apb_rtc_top/U_DW_apb_rtc_ic_U_DW_apb_rtc_write_sync0_rtc_clk_sync1_reg. (D11-1)
Information: There are 4 other cells with the same violation. (TEST-171)
Warning: Clock System_Reset connects to clock/clock inputs (SN/RN) of DFF u97_interface_mux_cntrl/u7_interface_top/u1_ahb_apb_bridge2_top/u4_apb_keypad_top/i_apb_keypad_timer/tick_divider_reg_16_. (D12-1)
Information: There are 19 other cells with the same violation. (TEST-171)
Warning: System_Reset clock path affected by new capture on LS input RN of DFF u97_interface_mux_cntrl/u7_interface_top/u0_ahb_apb_bridge1_top/u0_DW_apb_top/U_DW_apb_ahbsif_pwdata_int_reg_29_. (D15-1)
Source of violation: input RN of DFF u97_interface_mux_cntrl/u7_interface_top/u1_ahb_apb_bridge2_top/u7_tron_glue_logic_top/s_reset_reg_reg_0_.
Information: There are 20127 other cells with the same violation. (TEST-171)
Warning: Bus gate u97_interface_mux_cntrl/u7_interface_top/u1_ahb_apb_bridge2_top/u5_TRON_DAC/DAC_AOUT_0 failed contention ability check for drivers u_ioring_dac/pad_bottom_DAC_AOUT_0 and u97_interface_mux_cntrl/u7_interface_top/u1_ahb_apb_bridge2_top/u5_TRON_DAC/u_dac_0. (D20-1)
Information: There are 7 other cells with the same violation. (TEST-171)

---------------------------------------------------------------
DRC Report

Total violations: 41687

-----------------------------------------------------------------

67 MODELING VIOLATIONS
67 Cell has unknown model violations (TEST-451)

152 TOPOLOGY VIOLATIONS
90 Improperly driven three-state net violations (TEST-115)
62 Unconnected input pin violations (TEST-332)

41468 PRE-DFT VIOLATIONS
504 Uncontrollable clock input of flip-flop violations (D1)
1310 DFF set/reset line not controlled violations (D2)
19406 DFF set/reset line not controlled violations (D3)
64 Clock feeding data input violations (D10)
5 Clock feeding both clock and data input violations (D11)
20 Clock feeding multiple clock/set/reset inputs violations (D12)
20148 Clock path affected by clock captured by clock in level sensitive clock_port violations (D15)
11 Bus gate capable of contention violations (D20)


i am very new to dft field and a fresher too in professional field.. i am not able to understand what else i have to write in scripts other than this two lines to clear the violations..can you please help me to resolve this..? if you need any more information about my question i can give you..



Regards,
Rakesh
 

TonyLS

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If this is your first DFT project I suggest that you review scripts from past projects. Also visit the tool vendor's help pages, they usually have tutorials for new users. But in general there are other commands you need to provide to setup scan_enable, scan resets, and scan_mode.

For your particular problem, I would start by viewing the netlist and tracing the clock terminal of one of the flops that is violating to see why the top level clock port is not being connected to the flop. You may find that there is a clock mux that is being gated by a top level scan_mode signal that you need to take care of in your insertion script, I.E: set_dft_signal -view existing_dft -type Constant -active_state 1 -port SCAN_MODE
Another issue I have seen with D1 violations is that the clock_gating cell isn't being controlled properly in scan_mode, I.E the test_enable terminal of the clock gate isn't connected properly to the scan_enable pin.

Good Luck
 

RAKESH E.R

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Sir I also tried writing the scripts seeing the netlist using autofix commands this way, but i am unable to clear the violations still:: System_Test is the port used to control the both the clocks

########## use autofix to fix problems with resets and clocks ###############
### enable auto fix
set_dft_configuration -fix_reset enable -fix_clock enable
set_dft_signal -view spec -type TestMode -active_state 1 -port System_Test
### autofix clocks
# system clock
set_dft_signal -view spec -type TestData -port System_Clock
set_autofix_configuration -type clock -control System_Test -test_data System_Clock
# SCK_s
set_dft_signal -view spec -type TestData -port SCK_s
set_autofix_configuration -type clock -control System_Test -test_data SCK_s
### autofix resets
# System_Reset
set_dft_signal -view spec -type TestData -port System_Reset
set_autofix_configuration -type reset -method mux -control System_Test -test_data System_Reset
# CS_s
set_dft_signal -view spec -type TestData -port CS_s
set_autofix_configuration -type reset -method mux -control System_Test -test_data CS_s
######### end of autofix commands


please reply me if you can give any more suggestions.
 

honey13

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Hi Rakesh,

You need to define System_Reset, reset as type Reset, have you defined scan_enable?
 

RAKESH E.R

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Dear sir/madam..

yes i have defined all..
this was my script for "System_Reset and scan_enable"

###This is my DFT script::
#declare the scanclocks, resets, and scanenable signals
set_dft_signal -view exist -type ScanClock -timing {45 55} -port System_Clock
set_dft_signal -view exist -type ScanClock -timing {45 55} -port SCK_s
set_dft_signal -view exist -type Reset -active 0 -port System_Reset
set_dft_signal -view exist -type Reset -active 0 -port CS_s
set_dft_signal -view spec -type ScanEnable -active 1 -port CS_m

##report the scan signals specified
report_dft_signal
##create the test protocol
create_test_protocol -infer_clock -infer_async
##pre design rule check
dft_drc
################
after this i got again DRC violations then i wwent for autofix.. So can you tel me what can i do further to clear violations..
 

honey13

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Hi Rakesh,

Have you defined scan_in and scan_out's? If you have not mentioned any scan i/o ports define them by using following commands:

set_dft_signal -view_spec -type scandatain -port scan_in[1](scan input port)
set_dft_signal -view_spec -type scandataout -port scan_out[1] (scan output port)
set_scan_path -complete_false -scan_data_in scan_in[1] -scan_data_out scan_out[1]
 

RAKESH E.R

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Dear Honey,
Yes i have done that too.. this is my scripts
###declare scanin ports
set_dft_signal -view spec -type ScanDataIn -port SYNP_GPIO_A_15
set_dft_signal -view spec -type ScanDataIn -port SYNP_GPIO_B_0
set_dft_signal -view spec -type ScanDataIn -port SYNP_GPIO_B_1
set_dft_signal -view spec -type ScanDataIn -port SYNP_GPIO_B_2
set_dft_signal -view spec -type ScanDataIn -port SYNP_GPIO_B_3
set_dft_signal -view spec -type ScanDataIn -port SYNP_GPIO_B_4
set_dft_signal -view spec -type ScanDataIn -port SYNP_GPIO_B_5
set_dft_signal -view spec -type ScanDataIn -port SYNP_GPIO_B_6
set_dft_signal -view spec -type ScanDataIn -port SYNP_GPIO_B_7
set_dft_signal -view spec -type ScanDataIn -port SCL_s
set_dft_signal -view spec -type ScanDataIn -port SDA_s
set_dft_signal -view spec -type ScanDataIn -port LAMP_ON
set_dft_signal -view spec -type ScanDataIn -port IDT_GPIO_13
set_dft_signal -view spec -type ScanDataIn -port IDT_GPIO_14
set_dft_signal -view spec -type ScanDataIn -port IDT_GPIO_15
###declare scanout ports
set_dft_signal -view spec -type ScanDataOut -port SYNP_GPIO_A_0
set_dft_signal -view spec -type ScanDataOut -port SYNP_GPIO_A_1
set_dft_signal -view spec -type ScanDataOut -port SYNP_GPIO_A_2
set_dft_signal -view spec -type ScanDataOut -port SYNP_GPIO_A_3
set_dft_signal -view spec -type ScanDataOut -port SYNP_GPIO_A_4
set_dft_signal -view spec -type ScanDataOut -port SYNP_GPIO_A_5
set_dft_signal -view spec -type ScanDataOut -port SYNP_GPIO_A_6
set_dft_signal -view spec -type ScanDataOut -port SYNP_GPIO_A_7
set_dft_signal -view spec -type ScanDataOut -port SYNP_GPIO_A_8
set_dft_signal -view spec -type ScanDataOut -port SYNP_GPIO_A_9
set_dft_signal -view spec -type ScanDataOut -port SYNP_GPIO_A_10
set_dft_signal -view spec -type ScanDataOut -port SYNP_GPIO_A_11
set_dft_signal -view spec -type ScanDataOut -port SYNP_GPIO_A_12
set_dft_signal -view spec -type ScanDataOut -port SYNP_GPIO_A_13
set_dft_signal -view spec -type ScanDataOut -port SYNP_GPIO_A_14

## 6) insert scan paths
set_scan_path chain0 -view spec -scan_data_in SYNP_GPIO_A_15 -scan_data_out SYNP_GPIO_A_0
set_scan_path chain1 -view spec -scan_data_in SYNP_GPIO_B_0 -scan_data_out SYNP_GPIO_A_1
set_scan_path chain2 -view spec -scan_data_in SYNP_GPIO_B_1 -scan_data_out SYNP_GPIO_A_2
set_scan_path chain3 -view spec -scan_data_in SYNP_GPIO_B_2 -scan_data_out SYNP_GPIO_A_3
set_scan_path chain4 -view spec -scan_data_in SYNP_GPIO_B_3 -scan_data_out SYNP_GPIO_A_4
set_scan_path chain5 -view spec -scan_data_in SYNP_GPIO_B_4 -scan_data_out SYNP_GPIO_A_5
set_scan_path chain6 -view spec -scan_data_in SYNP_GPIO_B_5 -scan_data_out SYNP_GPIO_A_6
set_scan_path chain7 -view spec -scan_data_in SYNP_GPIO_B_6 -scan_data_out SYNP_GPIO_A_7
set_scan_path chain8 -view spec -scan_data_in SYNP_GPIO_B_7 -scan_data_out SYNP_GPIO_A_8
set_scan_path chain9 -view spec -scan_data_in SCL_s -scan_data_out SYNP_GPIO_A_9
set_scan_path chain10 -view spec -scan_data_in SDA_s -scan_data_out SYNP_GPIO_A_10
set_scan_path chain11 -view spec -scan_data_in LAMP_ON -scan_data_out SYNP_GPIO_A_11
set_scan_path chain12 -view spec -scan_data_in IDT_GPIO_13 -scan_data_out SYNP_GPIO_A_12
set_scan_path chain13 -view spec -scan_data_in IDT_GPIO_14 -scan_data_out SYNP_GPIO_A_13
set_scan_path chain14 -view spec -scan_data_in IDT_GPIO_15 -scan_data_out SYNP_GPIO_A_14
##############################

Still am not able to clear the violations, If you are not disturbed from my doubts please reply me what should i do..
 

honey13

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Run ATPG, as these are pre dft violations that occurs before inserting scan the tool can fix most of these warnings during scan stiching if your setup is properly done.
 

RAKESH E.R

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dear honey,
thank you very much. i will try to follow the same what you said..
 

RAKESH E.R

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Hi ,
Where do we have to set_scan_path?
After Pre DFT check or before creating protocol?
After declaring set_scan_configuration and set_scan_path do we have to do again create_test_protocol?
 

RAKESH E.R

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Run ATPG, as these are pre dft violations that occurs before inserting scan the tool can fix most of these warnings during scan stiching if your setup is properly done.

Hi honey, I am not working on Tetramax, Do we need tetramax tool To run ATPG ? Or how can i run ATPG?
I am very new to DFT so am not able to get the things easily..
 

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Tetramax is synopsys tool for ATPG. U require any one of the below tools to run ATPG.
Synopsys Tetramax
Mentor Testkompress.
I dont remember the name ot the tool but there is some tool from cadence also
 

RAKESH E.R

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Hi honey,
Is it required to study TCL and PERL for DFT?
 

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