How to choose the W/L of OPAMP differential pair

[lylnk]

increase gm by w / l

I have known that the voltage match is better if the Vdsat is small. I will make the W/L larger to achieve it.

If i use a pair of mos whose W/L is very large and Id is very small, the mos will be in the sub threshold region. How about the voltage match of the mos differential pair in sub threshold region. Is it better than mos in saturation region?:?:

 

[vinodkumar]

hi
think in other way to improve match becoz if u increase w/l to improve it.u r losing the basic idea of vlsi i.e., scaling.

 

[lylnk]

The analog circuit needs a lot of area.

I means the area of differential pair is not changed.

For example: the current is 1uA, the W/L of nmos is 50um/8um or 200um/2um. Which is better?

 

[invent]

Choosing the right size is a balancing act. Having a larger W/L wil cause your Id (as you already known) to drop. Parameters such as responce time and gain bandwidth will suffer.

Same as for the ratio, if W/L is 200µm/8µm it will be better than 50µm/2µm in terms of matching as they will vary less during wafer fabrication. However, this will significantly increase the chip size and therefore the cost.

 

[shaq]

Bigger is better!!

 

[aic_zh]

With the very small transistor, if you choose L < 1um, than all the formels for hand calculate have have an error of 40% ... ( you can see it in Cadence simulate ) . I think you should choose the bigger one for analog , because the analog needs a lot of area , and you can advoid many bad effect of short channel

 

[lylnk]

Bigger is better!!

W/L or AREA?

Added after 7 minutes:

I simulated a 3.3v nmos with 1uA Ids.

Changed the W/L while keep the area unchanged.
When the Vgs is 50mv higher than Vth, the gm is 14u.
When the Vgs is same with Vth, the gm is 16u.
When the Vgs is 50mv below Vth, and the gm is 19u.

Increase th W/L again, the gm increases small.

 

[laglead]

for differential input pair we does not consider their voltage match, but gm match instead.

 

[lylnk]

for differential input pair we does not consider their voltage match, but gm match instead.

I think the match of gm is not important. The match of Vgs of input different pair is most important. The match of Ids of current mirror is most important.

Consider a different pair, their Vgs is same when input is zero, their gm mismatch 10%. I think it works ok. The delta Ids depends on both the gm1 or gm2, the effective gm can be calculated.

 

[pkalavakuru]

Keeping Matching concept in mind , try to dimmension and Later u can trim reagrding bandwidth e.t.c (length = shouldnot be min lenght bcoz channel modulation and als matching depends on it )..

if diff pair is rail to rail ..make the dimmension s (NMOS Pair(2.5*)> PMOS pair)

 

[mists]

if diff pair is rail to rail ..make the dimmension s (NMOS Pair(2.5*)> PMOS pair)

I think it should be pmos pair > 2.5X nmos pair.

 

[kumard35b]

if you are using differential pair rail to rail you need to have bigger transistor and the both sizes of nmos and pmos should be of equal area ie 80/4 or bigger to make it very low offset in the monte carlo analysis process and mismatch...you need to compensate on your delay ...and the bias current...and the gm is kept constant....

 

[beckchm]

L is bigger when matching is requred.

vdsat is smaller when voltage matching is requred.

 

[lylnk]

L is bigger when matching is requred.

vdsat is smaller when voltage matching is requred.

I do not know what is the best vdsat.

Is 50mv is ok? or 0mv ( Vgs=Vth in level 49 model ) ?
-50mv ? Or make it as low as possible?

 

[mists]

for match, not L, but area is more important

 

[pkalavakuru]

In my mind it was PMOS 2.5* NMOS ..Sorry for it..It was myistake ..i ain't checked.dddd