How to choose the output drive current of I/O pad in ASIC

[john5888]

Anybody knows how to choose current of output for I/O pad of ASIC,
I have a design of ASIC, the vendor say their I/O pad have
1, 6, 8, 12, 24 mA, but I do not know how to choose it for my ASIC,
choose smaller, I am afraid it can not have enough drive capability,
choose larger, I am afraid it will cause ground bounce or make noise,
crosstalk etc.

What is the general rules for choose output drive current?

 

[shell3]

Selecting I/O cell is one of the critical step in ASIC design.
The selection is done according to the following:
1) External loading on the pin in pF
2) Timing requirement: Clock to out and setup/hold
3) In/Out requirement: 3.3V/5V, LVTTL, LVDS....
4) SSO (Simultaneous Switching Outputs) will affect
the power pin requirement.

Then use a Static Timing Analyser (P*rimeT*ime) to
verify your implementation.

 

[shockie]

Selecting I/O cell is one of the critical step in ASIC design.
The selection is done according to the following:
1) External loading on the pin in pF
2) Timing requirement: Clock to out and setup/hold
3) In/Out requirement: 3.3V/5V, LVTTL, LVDS....
4) SSO (Simultaneous Switching Outputs) will affect
the power pin requirement.

Then use a Static Timing Analyser (P*rimeT*ime) to
verify your implementation.

Why?
Could primetime verify the selceting I/O cell in anyways?
I don't konw,would you like describe it in details.

 

[shell3]

The I/O cells are subject to the same timing requirements
as the core cells. Consider an output cell: the timing arc
goes from a FlipFlop in the ASIC core to the input register
of an external device. The reverse apply for input cells.
For asynchronous path: IN to OUT delay need to meet
min/max propagation delay..

Basically you will create a script file for Pr*meT*me where
you specify the clock period, the external setup/hold required
by external device and the setup/hold for the ASIC inputs.

By specifying a Capacitive load on the the Outputs Pr*meT*me
will derate the propagation delay accordingly.

Now, the choice of I/O drive is done relavive to load driven
by an output and the expected lenght of the wire to connect
to the destination device. For CPU bus: 10 to 16ma, for point to
point connection: 4ma. You will select the minimum drive to
meet the timing and the Rule Checker (dv/dt ramping...).

Remember that it is as complicated to select the Input cells
than it is to select the Output cells. There is a race condition
between the inputs and the associated clock.

 

[radix]

You don't mention if the different strength drivers of the library that you're dealing with are of the same impedance. If the load that you're driving is PCB trace of sufficient length then you will need to match the driver impedance with the line to minimize reflections.

 

[shell3]

The ASIC library provides many types of I/O technology: TTL, LVTTL, LVDS, PECL ... so the impedance and voltage parameters are the one specific to the type you use. Line termination issues apply to ASIC as any other components, but PrimeTime is not the tool to analyse it. ASIC vendors provide IBIS models for analog simulation.

 

[radix]

The point I was trying to make is that you can't look at the timing numbers alone without considering the line impedance.

Even if you pick a technology type, the impedance of the driver varies with the drive strength. IBM's SA12E cell family for example has a set of drivers whose impedances range from 20-65 ohms. If you look at the timing numbers alone and end up selecting a 20 ohm driver to drive a 65 ohm line, you're still going to end up with crap.

radix