How to choose between various implementations for the same digital logic ?

[Goutham Kolluru]

Recently I ran into this wonderful case study.

https://www.quora.com/As-an-electri...l-for-the-rest-of-my-life/answer/Arijit-Layek

This is a small case study which discusses two implementations of the same digital logic (4-input AND gate). Basically I am looking for resources (technical papers/ books/ blogs/ ...... anything !!!) which throw some light on how should one choose a particular implementation from a choice of various gate-level implementations for the same digital logic. I did a small research on the internet but couldn't find any relevant material (I may be wrong) so I decided to post this here. Any help is greatly appreciated.

 

[artmalik]

Well you will not find anything!! Because the EDA tools end up doing all this. In any timing tool like EDI(cadence tool) or Design Compiler(Synopsys) will do it for you depending on the timing requirements. If there is one of the input pins which is coming in early it will use a structure which is late for this pin. It will optimize the gate structure, pin swapping(late vs early pin), gate drive strength, Vt type of the gate etc. The main goal is to meet the timing constraint ...in your and gate structure it will be (delay suppose it 5ns)....the tool will pick the implementation which will meet the delay of 5ns for each of the pin depending on the arrival times of various inputs.

 

[Goutham Kolluru]

yes, EDA tools do take care of most of the optimisation stuff. But as I am in the learning curve I want to predict the optimal model by myself (for small circuits obviously ). Just as we measure logical and electrical efforts to estimate delay, similarly are there any cheat sheets to estimate the parameters for other constraints too. I am looking for some resources to learn about these.

Thanks
goutham

 

[artmalik]

Well if you look at this from understanding point of view... it will take you to Graph theory and Boolean mathematics. For academic purpose you have hand_optimization, Karnaugh Maps, Quine-Mclusky algorithms. As the number of pins/gates and complexity increases...it is difficult to do this by "hand".....It is a good thing to understand the basics and after that it becomes a algorithm based data management....
You should see some of the lectures on youtube through NPTEL....on synthesis and digital design.....it will cover most of things that you are interested in......