How to choose a FPGA for adaptive filters?

[bercam]

dsp with FPGA

I'm trying to work with adaptative filters with FPGA. I'm thinking about low cost solution such us Cyclone and/or SpartanIII. I've some experience in uC and Dsp's but I don't know how exactly to work in FPGA.

There are dsp library, toolbox or VHDL code written?

Cyclone Ep1c12 have 20multipliers and SpartanXC3S200 have 12. Is this the mainly priority in order to select a device?.

Thanks in advance.

 

[lucbra]

Re: dsp with FPGA

Don't forget that in digital filters you will need to do MAC calculations. This means that you will consume considerable amount of logic in Cyclone or Spartan devices to implement your adder functions.
Take a look at Lattice newest introduced devices also. I'm already working on a design with ECP. Implementing a 1024FFT gives superior performance.
Things to consider:
Performance
Algorithm
Architecture
Price
Tools (Simulink)

 

[Beetroots]

Re: dsp with FPGA

Are you sure that Cyclone device has hardware multipliers?

It's a while since I looked at the Cyclone architecture but if I remember correctly it doesn't have any hardware multipliers - if thats the case you'd have to build them from the logic fabric, and 20 *soft* multipliers would probably use up all the device resources!

I'll have to go and dig out the data sheet.

 

[Aser]

Re: dsp with FPGA

Concerning adaptive filter,
I recommend you to build the data path
which implements a single stage of the filter
and the whole filter has to be calculated serially, ie.
N stages for N cycles.
Then the multiplier number will fit the device.
Another task is to calculate the prediction error.
For this task the proper data path is needed as well
which also derives the result for N cycles.
May be the lookup table is needed to calculate the
square root, etc.
You see that such behavioral is similar to DSP implementation
except that K commands of a single program iteration
are computed for a single clock cycle.

 

[bercam]

Re: dsp with FPGA

Relative to Cyclone multipliers I've seen this link about dsp features.

https://www.altera.com/products/devices/cyclone/features/cyc-dsp.html

Now my doubt is, these multipliers are a fixed structure or they're eating FPGA resourses for each implementation?

Have Simulink direct translation to big number of FPGA?, this implementation is worst than VHDL description?

 

[davorin]

Re: dsp with FPGA

Relative to Cyclone multipliers I've seen this link about dsp features.

h**p://www.@ltera.com/products/devices/cyclone/features/cyc-dsp.html

Now my doubt is, these multipliers are a fixed structure or they're eating FPGA resourses for each implementation?

Ehhm...you didn't read what is on the page...right????
It says clearly:

The Cyclone device's M4K blocks can be used to implement soft multipliers that provide high performance for a variety of low-cost applications such as image processing, audio processing, and consumer electronics systems.

And on the same page you see how much resources it uses!!!!!

The next-generation "Cyclone-II" have hardware multipliers.