Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] How to check un-clocked flops and how to trace the source point for the problem ?

Status
Not open for further replies.

purushotham.vlsi

Newbie level 3
Joined
Nov 2, 2019
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
30
How to check un-clocked flops and how to trace the source point for the problem ?
 

purushotham.vlsi

Newbie level 3
Joined
Nov 2, 2019
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
30
Could you possibly be more vague? We are not mind readers.

Here, I am asking that
After doing sanity check check_timing , we get to know that how many flops are not getting clocks. For that how to trace where the problem is ? and how to resolve it ?
 

ThisIsNotSam

Advanced Member level 5
Joined
Apr 6, 2016
Messages
2,178
Helped
382
Reputation
764
Reaction score
396
Trophy points
83
Activity points
11,128
Here, I am asking that
After doing sanity check check_timing , we get to know that how many flops are not getting clocks. For that how to trace where the problem is ? and how to resolve it ?

check your design, check your SDC. trivial debugging. missing a clock is huge.
 

ThisIsNotSam

Advanced Member level 5
Joined
Apr 6, 2016
Messages
2,178
Helped
382
Reputation
764
Reaction score
396
Trophy points
83
Activity points
11,128
by checking SDC , we won't get solution for this, I think. Can you please explain briefly.

You have made such a humongous mistake that it should not need any explanation. TRACE THE DAMN LOGIC. FIND WHERE THE CLOCK IS MISSING. How hard is this? Have you actually tried? What is stopping you?
 

dpaul

Advanced Member level 5
Joined
Jan 16, 2008
Messages
1,531
Helped
307
Reputation
614
Reaction score
308
Trophy points
1,373
Location
Germany
Activity points
11,405
How to check un-clocked flops and how to trace the source point for the problem ?

The problem shouldn't be coming to this stage. I would doubt the engineer who wrote the RTL!
How can the person write an RTL such that a clock is not connected to a flop?
 

oratie

Full Member level 6
Joined
Jan 10, 2007
Messages
348
Helped
176
Reputation
350
Reaction score
169
Trophy points
1,323
Activity points
3,696
Clock may be not declared in SDC. Even more, it can be generated inside the same module. So, no only RTL engineer is involved in this problem.
 

barry

Advanced Member level 5
Joined
Mar 31, 2005
Messages
5,267
Helped
1,129
Reputation
2,270
Reaction score
1,136
Trophy points
1,393
Location
California, USA
Activity points
28,830
Ridiculous. This is not a problem of “un-clocked flops”; it’s a problem of design. How do you know there are “un-clocked flops”? Did you run a simulation? if you put a signal in a clocked process, you’ll get a FF with a clock. How do you even GET a “un-clocked flop”??
 

oratie

Full Member level 6
Joined
Jan 10, 2007
Messages
348
Helped
176
Reputation
350
Reaction score
169
Trophy points
1,323
Activity points
3,696
As purushotham.vlsi has wrote - it is output of DC check_timing command. It lists all unclocked FFs.
 

ads-ee

Super Moderator
Staff member
Joined
Sep 10, 2013
Messages
7,846
Helped
1,815
Reputation
3,640
Reaction score
1,777
Trophy points
1,393
Location
USA
Activity points
59,265
If it is a check_timing command then there probably isn't a clock constraint defined for the clock. My guess would be it's a internally generated clock that requires a create_generated clock command to specify it's reference, source node, frequency, and duty cycle.

I think the OP needs to ask the person responsible for the RTL (that has this clock) and someone else with more experience in using DC.
 

purushotham.vlsi

Newbie level 3
Joined
Nov 2, 2019
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
30
Yes, Oratie Thank you.

By doing check_timing , we get to know that no. of flops which are not getting clock.
 

FvM

Super Moderator
Staff member
Joined
Jan 22, 2008
Messages
48,917
Helped
14,335
Reputation
28,933
Reaction score
13,080
Trophy points
1,393
Location
Bochum, Germany
Activity points
282,260
According to dc user manual, check_timing checks for unconstrained clocks (see post #11) and clock gating. Which warnings do you see for the respective FFs?
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top