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[SOLVED] How to check un-clocked flops and how to trace the source point for the problem ?

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purushotham.vlsi

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How to check un-clocked flops and how to trace the source point for the problem ?
 

purushotham.vlsi

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Could you possibly be more vague? We are not mind readers.

Here, I am asking that
After doing sanity check check_timing , we get to know that how many flops are not getting clocks. For that how to trace where the problem is ? and how to resolve it ?
 

ThisIsNotSam

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Here, I am asking that
After doing sanity check check_timing , we get to know that how many flops are not getting clocks. For that how to trace where the problem is ? and how to resolve it ?

check your design, check your SDC. trivial debugging. missing a clock is huge.
 

ThisIsNotSam

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by checking SDC , we won't get solution for this, I think. Can you please explain briefly.

You have made such a humongous mistake that it should not need any explanation. TRACE THE DAMN LOGIC. FIND WHERE THE CLOCK IS MISSING. How hard is this? Have you actually tried? What is stopping you?
 

dpaul

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How to check un-clocked flops and how to trace the source point for the problem ?

The problem shouldn't be coming to this stage. I would doubt the engineer who wrote the RTL!
How can the person write an RTL such that a clock is not connected to a flop?
 

oratie

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Clock may be not declared in SDC. Even more, it can be generated inside the same module. So, no only RTL engineer is involved in this problem.
 

barry

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Ridiculous. This is not a problem of “un-clocked flops”; it’s a problem of design. How do you know there are “un-clocked flops”? Did you run a simulation? if you put a signal in a clocked process, you’ll get a FF with a clock. How do you even GET a “un-clocked flop”??
 

oratie

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As purushotham.vlsi has wrote - it is output of DC check_timing command. It lists all unclocked FFs.
 

ads-ee

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If it is a check_timing command then there probably isn't a clock constraint defined for the clock. My guess would be it's a internally generated clock that requires a create_generated clock command to specify it's reference, source node, frequency, and duty cycle.

I think the OP needs to ask the person responsible for the RTL (that has this clock) and someone else with more experience in using DC.
 

purushotham.vlsi

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Yes, Oratie Thank you.

By doing check_timing , we get to know that no. of flops which are not getting clock.
 

FvM

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According to dc user manual, check_timing checks for unconstrained clocks (see post #11) and clock gating. Which warnings do you see for the respective FFs?
 
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