How to check throughput of Ethernet MAC IP Core 1G

[Guru59]

mac check ethernet speed

hi,
i have to work on Ethernet MAC IP core 1G from Opencores and i have to validate it on 88E1111 chip.
how can i check the throughput of the MAC core.
how to conclude whether i am getting 1Gbps speed or not.

thanks

 

[ljxpjpjljx]

check throughput mac tool

add checker in the IP !

 

[viv_1005]

where to check ethernet speed on mac

This is performance testing.
I believe that you will have two fifo's in your design. One on xmit side and one on rcv side.

Xmit side:
Your application has to provide data to xmit engine in such a way that xmit machine is not idle at any point of time. i.e the fifo is not empty or partial empty. Now with this scenario the xmit machine, with mim ipg should be able to send continuous packets.
You need to run this scenario for a longer duration. The checker should see continuous packets coming out on tx line with min ipg.

( I am assuming that data_width * clock_freq = 1G. i.e. if your data width is 8 bit then the clock should be 125 MHz. this will give you 1G)

Your application has to give data in such a way that the generated packets correspond to 1G speed. i.e. it needs to make sure that the packets created after adding the preamble, crc, ipg etc will correspond to 1G speed. if it does that then the fifo will never be full.

(I need to think more on this)

Rcv side:
Your receiver should be able to accept data at 1G rate. For that your driver should be continuously driving mac packets with min ipg for significant amount of time.
If the receive machine of the design does not generate a pause frame, of the receive fifo is not full, then you can say that your receiver is able to run at 1G speed.
Make sure that your application is draining the rx fifo continuously.

Probable observations are:
1. tx/rx fifo depth is not sufficient.
2. the fifo read is slower than write in case of rx. In this case you will encounter rx fifo full condition. this will not meet the performance requirements.
3. in tx case the fifo write is slower than fifo read. The fifo will be empty. in this case you will not be able test the performance correctly.