How to check LVS for such layout?

[chris_li]

Hi Guys, below is a portion snapshot of sub-block layout from P&R tool. Stdcell places back-to-back in each cellrow and power/gnd rail alternative supply stdcell.


For each power/gnd rail, VDD and VSS pin generated at the line end as illustrated left side, which is used to connect power/gnd net at top-level.


When run LVS by Calibre, those VDD and VSS extracted as separated ports, thus port number is not matching source's (note: source only has tow powre/gnd ports: VDD and VSS)


So, how to have Calibre identify rail pin "VDD" and "VSS" as only two ports?

 

[GI]

Hi Chris,

You may need to provide calibre power & ground names like below:

LVS POWER NAME "VDD"
LVS GROUND NAME "VSS"

Best regards,
Gokhan
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