How to check for two signal transitions in VHDL?

[msdarvishi]

Hello,

I am working on a design that I need to write an expression in VHDL to translate this statement :
"If the rising edge of CLK signal occurred and rising edge of another signal occured..., do something "

I wrote the following code :

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
process (clk, locked_sig_s, enable, latched_output, S1, S2, S3)
 
begin
        if (locked_sig_s = '1' and enable = '1') then
                if (RISING_EDGE(clk) then
                         if (RISING_EDGE(latched_output)) then
 
                                       S1 <= clk - latched_output_sig;
 
                         elsif (FALLING_EDGE(latched_output_sig(0))) then
 
                                       S2 <= latched_output_sig - clk;
 
...

---

I got the following error :

ERROR:Xst:827 - "/export/tmp/darvishi/xilinx/BASIC_FPGA_TDC_Design_Me_part_by_part/TDC_Complete_with_Renaud_PLL_with_LFSR_Comparison_New_Technique_Aug_17/observer.vhd" line 94: Signal S2 cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.
-->

I know that:

Writing in this style means that we must assort a D-FlipFlop being sensitive to two transitions that is not possible in FPGA hardware... But I am wondering there is way to do the statement in VHDL?

Thank in advance for your help

Regards,

 

[ads-ee]

XST can't synthesize it and you seem to understand that, so why are you trying to do this? If the point is to use it in simulation then you shouldn't be linting your code with XST. Modelsim or ISIM won't care and will simulate non-synthesizable descriptions, though what you've described won't work as this code requires the clock edges occur at the same time but offset in delta time so the latched_output can be seen.

Try

---

Code VHDL - [expand]
1
2
if (rising_edge(clk) or rising_edge(latched_output)) then
...

---

I think this will work, but I don't have time to check it.

 

[TrickyDicky]

This is not possible in any technology - you would need two rising edges to be exactly co-incident, which is never going to happen and would be affected by all sorts of factors.

Are you sure you dont want an edge detector circuit on the latched_output signal?

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
signal latched_output_r : std_logic;
 
process(clk)
begin
  if rising_edge(clk) then
    latched_output_r = latched_output;
 
    if latched_output_r = '0' and latched_output = '1' then
      --detected rising edge 
 
    elsif latched_output_r = '1' and latched_output = '0' then
      --detected falling edge

---

 

[wtr]

Expanding on #3.

What you want to do is then assign a strobe or tick (re_strb or fe_strobe) based on where you are in the edge detection circuit.

Then you use the strobe or tick in your conditional if statement.

such that

---

Code VHDL - [expand]
1
2
3
4
5
if (RISING_EDGE(clk) then
  if re_latched_output_strb = '1' then
  -- 
  elsif fe_latched_output_strb = '1' then
  --

---

I don't get the

S1 <= clk - latched_output_sig;

From my experience it is BAD practice to mix data tree signals and clock tree signals. During synthesis all sorts of crazy stuff happens, and this can lead to problems.
Consider the following.... inorder for S1 to be assigned during this stage you already know clk is '1'