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How to check for invalid data

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nesta

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Hi VhdlExperts,

Is there a way to check if the vector is uninitialsed 'U' or unknown 'X' as i have a scenario where i need to check for only valid data.

Basically I want to latch only valid data.

----
if(clk ='1' and clk'event) then
if(input = 'U' or input = 'X') then
-- just ignore;
else
-- latch the data;
end if;
end if;


Any suggestion plz,

Thanks in advance.
Nesta
 

std_match

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You can only do such things in simulation, not when you synthesize logic for real hardware. In real hardware you need another signal to indicate if the data is valid or not.
 
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sameh_yassin99

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Is there a way to check if the vector is uninitialsed 'U' or unknown 'X' as i have a scenario where i need to check for only valid data.
In software, we need to initialize variables because these values are stored in the program memory which may contain any previously stored values , so the term 'un-initialized' is valid.

In HDL languages it is different, we write code to be transferred to hardware, i.e. when you write a code for 2-input AND gate there is no meaning to initialize the inputs of the gate. You can fix the inputs of the gate to logic '0' or logic '1' but there is nothing that makes the input initially pulled low or high then it accepts normal inputs.

The logical values 'U' and 'X' can be used by simulation to indicate strange connections in your code only...

regards,
 

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