how to check BRAM availablity from the report in Xilinx ISE?

[xtcx]

Hi friends!, I am using Spartan 3 (2000K gate) chip for my project. Xilinx ISE 8.2i

Doubt No.1
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During running synthesis, under "Device utilization", it shows "BRAM = 38\40 - 95%"
When I further ran PAR, there under "Logic Distribution",it shows "No. of BRAMs =26\40 - 65%"

Now here, which one should I consider?...In synthesis report it showed 95%,
whereas here it shows only 65%...Can I use more BRAM by considering the PAR results? or should I watch out for synthesis report too?...That means,only "2" BRAMS couldbe used as compared to Synthesis report, but "14" couldbe used from PAR report...If I proceed by using more than 2, will it generate error?...Or what shouldbe done?...I don't know...

Doubt No.2
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Similar to the BRAM case, the maximum frequency value is shown in synthesis report as 57.3 MHz ,but where should I find the PAR clock result?.Also could someone tell me which one should be taken in to consideration
...Please help....Thanks.

 

[farhada]

Re: how to check BRAM availablity from the report in Xilinx

First of all, all information from synthesis are preliminary, not final. For the memory, it is probably so that the synthesis identifies some blocks in your design that are either removed by the place and route or optimized/replace with alternative logic.

For the frequency, again, the synthesis is "guessing" your maximum speed, if you have any XCF file (if you are using Xilinx's synthesis) then you will get a better report, but then again it is the PAR that reports the correct timing after the design is optimized and all unused logic removed.

One important issue is to look for warnings in your synthesis report and see if there are any missing signals in your sensitivity list, XST removes large parts of your logic if the signals are not in the sens-list of your process and that can explain the big difference in the sizes you see.

Hope you find this helpful,

Best regards,
/Farhad Abdolian

 

[xtcx]

Re: how to check BRAM availablity from the report in Xilinx

thanks friend!...but missing signals in sensitivity list, is only for simulation only...How can you say that missing signals in sensitivity list affects the signals in real time?.,,,,Any proof?...Thanks

 

[farhada]

Yes, but XST will remove a lot of logic inside your process if the signals are not in the sensitivity list of the process, the same goes for signals that are set in the if statement but missing in the else part of the same statement.

I had very different results using XST and other synthesis tools.

 

[xtcx]

Re: how to check BRAM availablity from the report in Xilinx

Thanks farhada, I am well understoos!...One more ,Could you please clarify about that BRAM case?....Iam getting almost full BRAM size in synthesis, but in implement, it takes only 65%...But if I continue to use more with 65% BRAM in my mind, the synthesis fails saying you have exceed the resources....Now what is the way to use the remaining 35% BRAM as shown in PAR?...Any idea?...It looks like catch22 situation...Any configuration or parameter that can be specified to bypass checking? ....Likewise...? thanks

 

[farhada]

Could you please send me your report files so I can look at it, send them to my e-mail f.abdolian(at)yahoo(dot)com

Cheers,
/Farhad