Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
@Kirangu, it's not clear at which you want your setup time to be negative, at your flop input pin or package input pin.
In either way,if you delay your clock line you can get a negative setup time. However, if your flop gets a negative setup time at its input, it will not work. If you maintain a negative setup time at package input (depending on the package specifications) , your flop may work.
Actually the sole purpose of giving a negative setup time is to compensate for the delay acquired by the clock line with respect to the data line.