Member level 5
I want to capture the first two consecutive edges of CLK after EN signal goes high. The following picture shows the idea. The thing that matters is that the difference between P1 and P2 must be exactly (up to 2% error is fine) one period of CLK. Since CLK oscillates at 2.4 GHz the difference between P1's and P2's edges should come up 417ps +/- 8ps. For that to happen the path from CLK to P1's output and from CLK to P2's output must be fully symmetric, something that looks hard to be met in practice? There are maybe a few ways to implement the idea but I don't know if there is a concrete solution to the problem. What you see below is my attempt at the solution:
module test( input EN, input CLK, output P1, output P2 ); reg [1:0] state; reg PR1, PR2; always @(posedge CLK) begin if (!EN) state <= 0; else state <= state+1; end always @(state) begin case (state) 2'b01: PR1 <= 1; 2'b10: PR2 <= 1; endcase end assign P1 = PR1; assign P2 = PR2; endmodule
The above code though works in pure RTL simulations it may not actually work in practice because of case conditions that may not suggest the same symmetric logic. Do you have an idea better than mine?