How to call a different language from Verilog?

[gigle]

I need a function that replaces some strings from existing file. Do you have any idea how to implement this function with Verilog.

Calling different language such as C or script should be OK. In this case, please let me know how to call different language from Verilog.

Example:
"file.i"
111
222
333
444
555

|
V

111
888
333
444
555

Thanks