How to calculate W/L ratio for given current

[bicave]

For example current 1uA,0.5uA,10uA flow through NMOS,PMOS.
What is the most suitable for W/L ratio?

 

[engrvip]

it depends upon the requirement of ur ckt. u cant decide to flow current randomly.And then knowin curr. an bias voltage of ur mos u can calculate sizes of transistor.

 

[vladimir1984]

Try to use this equation
Id=(K/2)(W/L)(Vgs-Vth)^2

 

[bicave]

suppose W/L=1/2. use choose
W=2;L=4
W=4;L=8
why W=5;L=5

The most suitable value for W/L?

 

[Karthikeya]

hi
when designing the current mirror you have to first decide the range of Vgs and W/L...ie upper and lower limits from the current eqn.
Next, from the given threshold variation of the MOS transistor decide the values of these two parameters optimizing for smallest area and smallest variation in current (due to variation in Vth)

regards

 

[YingChow]

Hi all,

I have doubt about the W/L for the current mirror also. From the equation id = K'(W/L)(Vgs-Vt)^2, the W/L ratio (eg W/L = 2) can have a lot of combinations. Is that any rule of thumb when designing the circuit? What are the effect in the circuit by using the same W/L ratio with different W n L values? Thanks in advance

 

[renwl]

Hi all,

I have doubt about the W/L for the current mirror also. From the equation id = K'(W/L)(Vgs-Vt)^2, the W/L ratio (eg W/L = 2) can have a lot of combinations. Is that any rule of thumb when designing the circuit? What are the effect in the circuit by using the same W/L ratio with different W n L values? Thanks in advance

match & impedance

 

[bill_sun]

trade off among these factors:matching,Ron,Noise,Vgs ,etc.

 

[shaikhsarfraz]

Hi,
If variable current like .5u,1u and 10u is flowing through the circuit than design the circuit for the worst case that is largest current.

Thanks
Shaikh Sarfraz

 

[usaid]

Greater value of W and L reduces the channel length modulation but contributes to parasitic capacitance and hence increases the RC delay.So take this fact into consideration.

 

[vijay_nag]

use Id=(K/2)(W/L)(Vgs-Vth)^2 keep Vgs-Vth >=100mV and take into account largest current that can flow

 

[YingChow]

Thanks for all the helps provided

 

[laglead]

For example current 1uA,0.5uA,10uA flow through NMOS,PMOS.
What is the most suitable for W/L ratio?

It depends the voltage headroom you have.

 

[tekno1]

I am surprised that nobody mentioned transistors operating point. W/L and current also decide transistors operating point which is very important (saturation, subthreshold linear operating regions in MOS). For operating in a targeted region designer have freedom of chosing w/l and current. MOS transistor with large W/L may put transistor in linear region ( degrading current matching or offset severely for example). Also all being in saturation region; amplifier inputs require large w/l versus current mirrors require small w/l so that offset/current matching will be smaller (gm - gain higher at inputs). If we continue... lower noise and offset requirements fawor large w large l. High output impedance reguires large l. ....

Anyways it must be clear by now that operating point and what is required from transistor to meet specifications prety much mandates w and l, current etc. Here of cource among a band of possible range of values designer selects smaller overall size (w/l) transistor for cost reasons.

This is just a few things to write into small window without much thinking (not complete coverage in any means) so please take this as some info and consider many other details and associated requirements (voltage, speed etc.) - design is mainly making trade offs. Even in a real design (for even every single seemingly similar designs) one considers a simpple solution and builds upon it the whistles and bells to make the final design after (hopefully) considering all necessary cases and constraints. I hope this helps.

A good analog book basicallly goes through these within the context of diff amp, current mirror etc. designs while mentioning a specific requirement (like offset).

 

[ptoo30]

addition to upward guys opinion
you may consider the variation caused from the etching error.
you need the device data showing (1/(sq root W*L))
and you need some effort to find proper L to keep the ratio if Id.