Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

how to calculate the path delay

Status
Not open for further replies.

xiongdh

Member level 4
Joined
Jul 18, 2002
Messages
76
Helped
2
Reputation
4
Reaction score
1
Trophy points
1,288
Location
china mainland
Activity points
682
In the sdf file.you can see the net delay and cell delay.when simulation,How to calulate the path delay by simulator.does it just simply add the delay of all the nets and cells through the path.
thanks
 

I think you want to compute the critical path of your design. The synthesis tools reports it . Usually, these kinds of data are extracted by synthesis tools not simulators. But in simulator, you can apply some testbeches to the design which activate the specified path by the synthesis tool. In simulator, you can see the waveforms which show the global delays (addition of net and component delays).

Regards,
KH
 

You can read the netlist and sdf to Primtime , then use Primetime report it!
 

I know that simulators can do that ,but how do the tools do that ? just only add?
 

What i have studied in a course entitled "algorithms to do automatic VLSI design", they are added to eachother. In other words, a RC model of wires will compute the delay of wires and the result will be added to the component delays to compute a path delay in an ASIC design.

Regards,
KH
 

xiongdh said:
I know that simulators can do that ,but how do the tools do that ? just only add?
yes,I think so. Simulation tool can backannotate sdf file into netlist with it's PLI.
each std.cell or each net should be correctly backannotated.
some kind of mismatch will terminate back-annotated.
 

sdf file can provide a not so precise path delay , after p&r , parameter extraction can provide more precise path delay info !
 

i think so. simulator just only add all of delays because it 's SDF file, NOT SPEC.
but for DC or PT, you can use report_delay_caculation to know that how to caculate delay for tools
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top