How to calculate setup and hold time of DFF ?

[mahantesh.pc]

Hi,
Please tell me how to calculate setup and hold time for TSPC based DFF

Specifications are,

Time Period ( T ) = 500 ps
Delay : < 250ps(*50% of T)
I/P rise time / fall time : 50ps(10% of T)

 

[erikl]

These depend very much on the structure of the TSPC FF, more exactly on the propagation delays of the transistors responsible for the activation resp. deactivation for Data and Clock, on their W/L ratios and their parasitic routing connection capacitances. See this example schematic from Wikipedia.

So you can only calculate/estimate these times if you know all the corresponding values for the specific TSPC FF. In order to get really reasonable results, usually simulation tools are used, together with extracted layout parasitics and reliable transistor models.

 

[dick_freebird]

I would not try to calculate S/H times from such datasheet
type values, if I was anywhere close to the performance
limits.

If you slide data edge across clock edge, you will see a
region where prop delay blows out, then metastability,
then fail-to-catch.

If you are going to depend on static timing analysis for
design closure, then your real setup-time-driven delay
needs to not break out of the timing model plus margin.
Some setup-time position will break out. You need to
respect this, following having determined the setup time
that causes timing breakout. That's not a calculation,
it's simulations, multiple, across cases and corners to
find a worst case that you will then push into the timing
model as a constraint for setup time that makes the
rest of the timing model, valid.