How to calculate offset voltage in clocked comparator

[jayapraksh]

hai all, I have designed a conventional dynamic and a double tail comparator in 180nm tecnology. To measure the offset voltage I did DC analysis by setting one of my input at .9V and other as a ramp signal of amplitude 1.8V. The clock frequency is 500 MHz and the supply voltage is 1.8V. I got the transient analysis as expected. But in the DC analysis the curve swings between 7nV and 8nV. Is there any fault in the method that I have followed. I don't understand what the problem is. This procedure worked for preamplifier based comparator. Do I need to follow any other method for clocked comparators? I am designing my circuit in Mentor Graphics. Please do help me to sort out this problem..

 

[dick_freebird]

You are going to have "binning" of results due to the clock
and the only way to better resolution is a slower ramp or a
feedback test loop (attenuator and integrator).

 

[jayapraksh]

Could you please elaborate on feedback test loop?

 

[dick_freebird]

https://www.edn.com/electronics-blogs/analog-ic-startup/4403529/The-op-amp-test-loop

 

[jayapraksh]

Thank you for your help.