How to calculate maximum frequency of a circuit?

[kumar_eee]

How to calculate the max.freq of the ckt?...

The delay between 2 adjacent flip-flops + Delay of combo

Is it correct?....

 

[anjali]

Re: Max frequency

generate reports with a clk period of zero.

then max freq = 1/max delay in the design

 

[kermit]

Re: Max frequency

kumar_eee:

The max frequency is calcuated like this:


tp = tsu + td + max(tco, th)


tp: period of the clock frequency
tsu: flip-flop setup time
td: the delay include wire delay, combine logic delay
tco:the clock to output delay of flip-flop
th: the hold time of flip-flop
max(tco, th) : the maximum between tco and th.

 

[carrot]

Re: Max frequency

Hi Kermit,

You said,
The max frequency is calcuated like this:
tp = tsu + td + max(tco, th)

Suppose assume,
tsu: 1ns
td: 3ns
tco:1ns
th: 2ns
max(tco, th) : the maximum between tco and th. - is it max(1,2)=2 ?????
tp: ?

My question is where exactly this setup-time in this equation comes in to play, because what i have read is hold time is independent of clock frequency. Then how come hol-time(th) has come into this equation?

Added after 1 minutes:


CORRECTION

My question is where exactly this hold-time in this equation comes in to play, because what i have read is hold time is independent of clock frequency. Then how come hol-time(th) has come into this equation?

 

[Nandy]

Re: Max frequency

In the view point of waveform, Setup time edge should be at the front of hold time edge. In other word, setup time edge and hold time
comprise a window which has left edge as setup edge. This window is
data transition forbidden window. When inside window, it would violate
setup or hold time.
So left side edge(setup edge) is where the fastest the logic can run which means setup timing plays role in determining max Freq not hold time.

Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode.

 

[dpk_tottempudi]

Re: Max frequency

setuptime plays role in performance of system
but if we wont meet hold , system will fail. so hold time plays role in functionality itself rather than performance.

what i mean to say is even if by some chance u don't meet setup after tapeout of the chip, because of changes in delay beause of temp changes caused by dynamic power diipitation...we will have option. beacuse we will have option to set the frequency at which chip has to run.

 

[bansalr]

Re: Max frequency

The Maximum frequency of operation is determine by the slowest path or the worst case delay.so it is the summition of the
t clock to q delay + combo delay and setup time of the other flop.
But while analysis we have consider the best case where hold time comes into picture. If for the given maximum frequency the
T(hold) <= t(combo delay) + t(clock to q delay) . If this eqation doesn't satisfy then circuit will fail. and in this case we have introduce the buffer in the data path to increase the delay . which will automatically decrease the frequency of operation.

Added after 2 minutes:

The Maximum frequency of operation is determine by the slowest path or the worst case delay.so it is the summition of the
t clock to q delay + combo delay and setup time of the other flop.
But while analysis we have consider the best case where hold time comes into picture. If for the given maximum frequency the
T(hold) <= t(combo delay) + t(clock to q delay) . If this eqation doesn't satisfy then circuit will fail. and in this case we have introduce the buffer in the data path to increase the delay . which will automatically decrease the frequency of operation.

 

[Yun Lin]

Max frequency

Generally it is that. But don't miss the setup and hold constrain.

 

[anjali]

Re: Max frequency

Hi Kermit,

You said,
The max frequency is calcuated like this:
tp = tsu + td + max(tco, th)

actually tp > tsu + td + tco-max

why th is comming into picture?

 

[elecs_gene]

Re: Max frequency

hi
th comes into picture only when ur hold time is more than clk2q delay in ur FF.under,such a condition,ur data should not change for that hold time part as well.so,i hope u get why hold time comes up in the picture..

regards

 

[anjali]

Re: Max frequency

still, i can't convince that " Th " comes into picture for setup violations.

can anybody provide material or link for that explanation..

 

[blanket]

Re: Max frequency

Hold time needn't come into the equation. The maximum time that your combination logic can take to do its computation is only limited by setup, skew, clk-2-Q delay and the time period of the clock signal.

This is the reason why on increasing time period of the clocking signal you can actually correct the operation of a circuit that was faulty because it couldn't meet set up time.

However, all said and done, the minimum time that your combinational logic should take to compute (if not computation, at least put a dummy delay) is a functional of skew, clk-2-Q delay and the hold time.

Hope this clarifies

 

[Resistance]

Re: Max frequency

hi ,

the freq at which the circuit does not violate set up time with ur consyaints well defined gives u ur max freq..

Max freq is adjacent flop delay plus comb delay..

Adjacent flop delay include c2q delay and setup time.. thats it..

regards