how to calculate input to output delay

[Al Farouk]

Currently I design a protocol conversion using X/ilinx FPGA some signals need to be passed through the FPGA and other can be dirctly connected, I'm worry about the time delay between the signals passed through FPGA and the direct ones and I should issue the PCB design now as it take long period to be back. my question is
1- Should I pass all signal through FPGA even no processing will be don on it?
2- How can I calculate the delay between an input and its corresponding output ?
3- How can I mnimize the delay for unproccessed signals? shuold I go through FPGA editor to manually assign the I/O pads for this signals or can I guid the synthesizer through VHDL coding and constraints file?

 

[dll_embed]

This is not a easy problem as it looks like. I'll try to give my 2 cents:
Generally you have a right concern here. Passing all signal through FPGA will add in delay in the loop. It may be above 10ns depending on your FPGA grade and layout. If the original signaling is synchrous and need feed back from other end, this add in delay may violate the setup time.
So you have to make sure the add in delay is acceptable.
So my answer to your question is:

1. Depends on your signaling protocol and delay of passing through FPGa.
2. You can make a simple program, just to pass through your signal. And do a place& route, then take a look at the timing report. From there you can get a more accurate delay information.
3. To assign IO pads, UCF file is enough to do that. The syntax is
NET sig_name LOC = "pad_name";

Hope this helpful!

regards

 

[Al Farouk]

regarding using LOC attribute to assign an I/O pin it will only assign the port but it will not add constraints to the logic that drive this pad to as close as possible to the port to minimize the delay, is ther any further constriants applied to the logic drive the port ?

 

[dll_embed]

As you only pass through the signal, it will consume only routing resource. And i don't think we can contraint to use a specific routing resource. But if you want to constraint the logic(can be mapped to CLB), maybe 'AREA_GROUP' can be used.

To minimise pad to pad delay, you can use inpad to outpad constraint.

**broken link removed**