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Hi! i wrote verilog code for low power test pattern generation and i have to apply the test pattern for benchmark circuits and calculate fault coverage how to find out fault coverage in cadence tool kindly some one help me
In general, fault coverage is calculated as the ratio of faults detected by your test patterns vs. the total number of possible faults. You need fault simulation for this. Im not familiar with Cadence tool, just give you some hints, try to research more.