Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

how to calculate delay in cadence?

Status
Not open for further replies.

muffassir

Member level 3
Joined
Sep 15, 2011
Messages
67
Helped
10
Reputation
20
Reaction score
10
Trophy points
1,288
Location
Planet Earth
Activity points
1,802
how to calculate the delay of inverter rc extracted layout ..

i calculated the delay from test ckt schematic ..

i want to calc the delay after rc extraction to see the effects of RC components on inverter (from rc extracted layout view)

please give the steps from which view i should start.??

Thanks in advance!!
 

If this is Assura, then you first need a clean LVS, then you run RCX, then you
prepare the av_analog_extracted view, then create the config view for your
simulation testbench; open it, start analog environment and select that view
for the inverters and then proceed with simulating.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top