Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

how to calculate breakdown of lateral dmos?

Status
Not open for further replies.
E

electronrancher

Advanced Member level 1
Joined
Mar 24, 2002
Messages
447
Helped
46
Reputation
92
Reaction score
11
Trophy points
1,298
Activity points
6,935
this one is tricky - how does drift region affect it? i want bvdss with gate grounded. who punches through first? i'm having hard time with this.

please, if you don't know what a lateral dmos is - plz don't clog this post. thx!
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top