How to caculate the PLL filter?

[brian39]

I have a RFIC for handphone. There is a PLL filter exteral to chip. how

can i caculate this filter , such as bandwidth , etc. Is there some reference

for it. THKS in advance.

 

[flatulent]

data sheet

The data sheet should have the details. If not you need all of the gain constants for the blocks in the loop. From here there are many ways. Someone should have a link to a calculator. I do the design using Bode plots myself.

 

[toonafishy]

Do it online...

***.national.com/appinfo/wireless/

 

[brmadhukar]

Hi,
You need to know few components for designing. Check the phase noise that is desired, of the oscillator from which you can arrive at the required loop badwidth assuming settling time is sufficient. Then with the help of the equations the component values may be arrived at. Some time Kph and Kvco may not be available. Kph = phase detector gain = supply/2/pi and Kvco must be determined experimentally.
For specifics of circuit PM with details

 

[adanshen]

if you have a ic, then you should have it's spec, and it will tell you what to connect

 

[FANT]

There is a very good article on EDN EUROPE, October 2000 pages 64, 65 and 66.
Now a scanner is not available, but tonight I think I will do it.
Wait for 6 Hours.
Mandi

 

[brian39]

Thanks!

 

[AL0117]

Read the book frfom Dean Banerjee. U can download it from the National website:
**broken link removed**

Cheers, Al

 

[AL0117]

Or you can try the site of Lance Lascari

http://tools.rfdude.com/PLL/pll.html

There are 2 articles published in AMW, and a pll calculation worksheet in mathcad

Al

 

[brian39]

Thanks a million !

 

[zcr35]

Have a look at this

in National.com from NS, AN1001.pdf has some detailed calculation. do it yourself, or use EDA soft such as Eagleware/PLLSim

 

[borich_03]

These are 3 articles, where you can find a simple teory and some examples about designing PLL sinthesizers.

Good luck!