Hi, All
could anybody provide me a good simulation method for efficiency. I could not simulate the full circuit just for efficiency, it is too time-consuming.
Back to calculation, I do not care about the power consuming for the swithing of gate of power transistor, which belongs to the core circuit power consuming and has no dependence with load current and input voltage level. I think besides the power lost on the resistor of swith and parasitic resistor, the charge and discharge of the drain capacitor and diode capacitor also contribute some power consume. And, I am not sure about the effect of rise time and fall time of clock.
I drawed a simple boost DCDC modulator as an example. the Vurneg is 4v, and the Vout is 12v. I think when the switch on, curent of coil increased. then switch off, firstly, in order the chage the positive node voltage of diode to 12+0.7V, the three capacitor has to be charged. This need some energy. But I am wondering, after the coil current reach zero, the energy stored in the parasitic capacitor go back to Vunreg until the drain voltage reach to Vunreg. And after that, switch on, and the capacitor is dischared to ground ,this dischared charge is really the lost of power.
Am I right?